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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02003 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
wdenk2262cfe2002-11-18 00:14:45 +00004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +00006 */
7
wdenk3bac3512003-03-12 10:41:04 +00008#ifndef _U_BOOT_I386_H_
9#define _U_BOOT_I386_H_ 1
wdenk2262cfe2002-11-18 00:14:45 +000010
Bin Meng002610f2015-06-07 11:33:13 +080011extern char gdt_rom[];
12
wdenk2262cfe2002-11-18 00:14:45 +000013/* cpu/.../cpu.c */
Simon Glass8b37c762014-11-06 13:20:06 -070014int arch_cpu_init(void);
Graeme Russ0ea76e92011-02-12 15:11:35 +110015int x86_cpu_init_f(void);
Graeme Russ1c409bc2009-11-24 20:04:21 +110016int cpu_init_f(void);
Graeme Russ9e6c5722011-12-31 22:58:15 +110017void setup_gdt(gd_t *id, u64 *gdt_addr);
Bin Meng002610f2015-06-07 11:33:13 +080018/*
19 * Setup FSP execution environment GDT to use the one we used in
20 * arch/x86/cpu/start16.S and reload the segment registers.
21 */
22void setup_fsp_gdt(void);
Graeme Russd6532442011-12-27 22:46:43 +110023int init_cache(void);
Gabe Blackf30fc4d2012-10-20 12:33:10 +000024int cleanup_before_linux(void);
Graeme Russ8c63d472009-02-24 21:14:45 +110025
26/* cpu/.../timer.c */
27void timer_isr(void *);
28typedef void (timer_fnc_t) (void);
29int register_timer_isr (timer_fnc_t *isr_func);
Simon Glasse761ecd2013-04-17 16:13:36 +000030unsigned long get_tbclk_mhz(void);
31void timer_set_base(uint64_t base);
Simon Glassd0b6f242013-04-17 16:13:39 +000032int pcat_timer_init(void);
Graeme Russ8c63d472009-02-24 21:14:45 +110033
Graeme Russabf0cd32009-02-24 21:13:40 +110034/* cpu/.../interrupts.c */
35int cpu_init_interrupts(void);
36
Simon Glasse1ffd812014-11-06 13:20:08 -070037int cleanup_before_linux(void);
38int x86_cleanup_before_linux(void);
39void x86_enable_caches(void);
40void x86_disable_caches(void);
41int x86_init_cache(void);
42void reset_cpu(ulong addr);
43ulong board_get_usable_ram_top(ulong total_size);
44void dram_init_banksize(void);
Simon Glass727c1a92014-11-10 18:00:26 -070045int default_print_cpuinfo(void);
Simon Glasse1ffd812014-11-06 13:20:08 -070046
Simon Glass447f8b02015-01-27 22:13:42 -070047/* Set up a UART which can be used with printch(), printhex8(), etc. */
48int setup_early_uart(void);
49
Graeme Russ79ea6b82010-04-24 00:05:48 +100050void setup_pcat_compatibility(void);
51
wdenk7a8e9bed2003-05-31 18:35:21 +000052void isa_unmap_rom(u32 addr);
53u32 isa_map_rom(u32 bus_addr, int size);
54
Graeme Russfea25722011-04-13 19:43:28 +100055/* arch/x86/lib/... */
wdenk7a8e9bed2003-05-31 18:35:21 +000056int video_bios_init(void);
wdenk2262cfe2002-11-18 00:14:45 +000057
Bin Mengaefaff82015-06-07 11:33:14 +080058/* arch/x86/lib/fsp/... */
59int x86_fsp_init(void);
60
Graeme Russf48dd6f2012-01-01 15:06:39 +110061void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
62void board_init_f_r(void) __attribute__ ((noreturn));
wdenk2262cfe2002-11-18 00:14:45 +000063
Bin Mengafbf1402015-04-24 18:10:06 +080064int arch_misc_init(void);
65
Vadim Bendebury2f899e02012-10-23 18:04:32 +000066/* Read the time stamp counter */
Simon Glassd8819f92013-06-11 11:14:52 -070067static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
Vadim Bendebury2f899e02012-10-23 18:04:32 +000068{
69 uint32_t high, low;
70 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
71 return (((uint64_t)high) << 32) | low;
72}
73
74/* board/... */
75void timer_set_tsc_base(uint64_t new_base);
76uint64_t timer_get_tsc(void);
77
Simon Glass65dd74a2014-11-12 22:42:28 -070078void quick_ram_check(void);
79
Simon Glassbcb0c612015-04-29 22:26:01 -060080int x86_init_cpus(void);
81
Simon Glassbdc88d42014-12-29 19:32:24 -070082#define PCI_VGA_RAM_IMAGE_START 0xc0000
83
wdenk3bac3512003-03-12 10:41:04 +000084#endif /* _U_BOOT_I386_H_ */