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gerrit.cesnet.cz / github / trini / u-boot / 7daf2ebe9196dd67131a06d85049c3a8a08ca413 / . / cpu / mips / start.S
blob: 09e4aab2505957014732b7be7f3c9df2c41887cf [file] [log] [blame]
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]1/*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]25#include <config.h>
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]26#include <asm/regdef.h>
27#include <asm/mipsregs.h>
28
Shinya Kuribayashidecaba62008-03-25 21:30:07 +0900[diff] [blame]29 /*
30 * For the moment disable interrupts, mark the kernel mode and
31 * set ST0_KX so that the CPU does not spit fire when using
32 * 64-bit addresses.
33 */
34 .macro setup_c0_status set clr
35 .set push
36 mfc0 t0, CP0_STATUS
37 or t0, ST0_CU0 | \set | 0x1f | \clr
38 xor t0, 0x1f | \clr
39 mtc0 t0, CP0_STATUS
40 .set noreorder
41 sll zero, 3 # ehb
42 .set pop
43 .endm
44
45 .macro setup_c0_status_reset
46#ifdef CONFIG_64BIT
47 setup_c0_status ST0_KX 0
48#else
49 setup_c0_status 0 0
50#endif
51 .endm
52
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]53#define RVECENT(f,n) \
54 b f; nop
55#define XVECENT(f,bev) \
56 b f ; \
57 li k0,bev
58
59 .set noreorder
60
61 .globl _start
62 .text
63_start:
64 RVECENT(reset,0) /* U-boot entry point */
65 RVECENT(reset,1) /* software reboot */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]66#if defined(CONFIG_INCA_IP)
67 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
68 .word 0x00000000 /* phase of the flash */
69#elif defined(CONFIG_PURPLE)
70 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
71 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]72#else
73 RVECENT(romReserved,2)
74#endif
75 RVECENT(romReserved,3)
76 RVECENT(romReserved,4)
77 RVECENT(romReserved,5)
78 RVECENT(romReserved,6)
79 RVECENT(romReserved,7)
80 RVECENT(romReserved,8)
81 RVECENT(romReserved,9)
82 RVECENT(romReserved,10)
83 RVECENT(romReserved,11)
84 RVECENT(romReserved,12)
85 RVECENT(romReserved,13)
86 RVECENT(romReserved,14)
87 RVECENT(romReserved,15)
88 RVECENT(romReserved,16)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]89 RVECENT(romReserved,17)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]90 RVECENT(romReserved,18)
91 RVECENT(romReserved,19)
92 RVECENT(romReserved,20)
93 RVECENT(romReserved,21)
94 RVECENT(romReserved,22)
95 RVECENT(romReserved,23)
96 RVECENT(romReserved,24)
97 RVECENT(romReserved,25)
98 RVECENT(romReserved,26)
99 RVECENT(romReserved,27)
100 RVECENT(romReserved,28)
101 RVECENT(romReserved,29)
102 RVECENT(romReserved,30)
103 RVECENT(romReserved,31)
104 RVECENT(romReserved,32)
105 RVECENT(romReserved,33)
106 RVECENT(romReserved,34)
107 RVECENT(romReserved,35)
108 RVECENT(romReserved,36)
109 RVECENT(romReserved,37)
110 RVECENT(romReserved,38)
111 RVECENT(romReserved,39)
112 RVECENT(romReserved,40)
113 RVECENT(romReserved,41)
114 RVECENT(romReserved,42)
115 RVECENT(romReserved,43)
116 RVECENT(romReserved,44)
117 RVECENT(romReserved,45)
118 RVECENT(romReserved,46)
119 RVECENT(romReserved,47)
120 RVECENT(romReserved,48)
121 RVECENT(romReserved,49)
122 RVECENT(romReserved,50)
123 RVECENT(romReserved,51)
124 RVECENT(romReserved,52)
125 RVECENT(romReserved,53)
126 RVECENT(romReserved,54)
127 RVECENT(romReserved,55)
128 RVECENT(romReserved,56)
129 RVECENT(romReserved,57)
130 RVECENT(romReserved,58)
131 RVECENT(romReserved,59)
132 RVECENT(romReserved,60)
133 RVECENT(romReserved,61)
134 RVECENT(romReserved,62)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]135 RVECENT(romReserved,63)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]136 XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
137 RVECENT(romReserved,65)
138 RVECENT(romReserved,66)
139 RVECENT(romReserved,67)
140 RVECENT(romReserved,68)
141 RVECENT(romReserved,69)
142 RVECENT(romReserved,70)
143 RVECENT(romReserved,71)
144 RVECENT(romReserved,72)
145 RVECENT(romReserved,73)
146 RVECENT(romReserved,74)
147 RVECENT(romReserved,75)
148 RVECENT(romReserved,76)
149 RVECENT(romReserved,77)
150 RVECENT(romReserved,78)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]151 RVECENT(romReserved,79)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]152 XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
153 RVECENT(romReserved,81)
154 RVECENT(romReserved,82)
155 RVECENT(romReserved,83)
156 RVECENT(romReserved,84)
157 RVECENT(romReserved,85)
158 RVECENT(romReserved,86)
159 RVECENT(romReserved,87)
160 RVECENT(romReserved,88)
161 RVECENT(romReserved,89)
162 RVECENT(romReserved,90)
163 RVECENT(romReserved,91)
164 RVECENT(romReserved,92)
165 RVECENT(romReserved,93)
166 RVECENT(romReserved,94)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]167 RVECENT(romReserved,95)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]168 XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
169 RVECENT(romReserved,97)
170 RVECENT(romReserved,98)
171 RVECENT(romReserved,99)
172 RVECENT(romReserved,100)
173 RVECENT(romReserved,101)
174 RVECENT(romReserved,102)
175 RVECENT(romReserved,103)
176 RVECENT(romReserved,104)
177 RVECENT(romReserved,105)
178 RVECENT(romReserved,106)
179 RVECENT(romReserved,107)
180 RVECENT(romReserved,108)
181 RVECENT(romReserved,109)
182 RVECENT(romReserved,110)
183 RVECENT(romReserved,111)
184 XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
185 RVECENT(romReserved,113)
186 RVECENT(romReserved,114)
187 RVECENT(romReserved,115)
188 RVECENT(romReserved,116)
189 RVECENT(romReserved,116)
190 RVECENT(romReserved,118)
191 RVECENT(romReserved,119)
192 RVECENT(romReserved,120)
193 RVECENT(romReserved,121)
194 RVECENT(romReserved,122)
195 RVECENT(romReserved,123)
196 RVECENT(romReserved,124)
197 RVECENT(romReserved,125)
198 RVECENT(romReserved,126)
199 RVECENT(romReserved,127)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]200
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]201 /* We hope there are no more reserved vectors!
202 * 128 * 8 == 1024 == 0x400
203 * so this is address R_VEC+0x400 == 0xbfc00400
204 */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]205#ifdef CONFIG_PURPLE
206/* 0xbfc00400 */
207 .word 0xdc870000
208 .word 0xfca70000
209 .word 0x20840008
210 .word 0x20a50008
211 .word 0x20c6ffff
212 .word 0x14c0fffa
213 .word 0x00000000
214 .word 0x03e00008
215 .word 0x00000000
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]216 .word 0x00000000
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]217/* 0xbfc00428 */
218 .word 0xdc870000
219 .word 0xfca70000
220 .word 0x20840008
221 .word 0x20a50008
222 .word 0x20c6ffff
223 .word 0x14c0fffa
224 .word 0x00000000
225 .word 0x03e00008
226 .word 0x00000000
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]227 .word 0x00000000
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]228#endif /* CONFIG_PURPLE */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]229 .align 4
230reset:
231
232 /* Clear watch registers.
233 */
234 mtc0 zero, CP0_WATCHLO
235 mtc0 zero, CP0_WATCHHI
236
Shinya Kuribayashid43d43e2008-03-25 21:30:07 +0900[diff] [blame]237 /* WP(Watch Pending), SW0/1 should be cleared. */
238 mtc0 zero, CP0_CAUSE
239
Shinya Kuribayashidecaba62008-03-25 21:30:07 +0900[diff] [blame]240 setup_c0_status_reset
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]241
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]242 /* Init Timer */
243 mtc0 zero, CP0_COUNT
244 mtc0 zero, CP0_COMPARE
245
246 /* CONFIG0 register */
247 li t0, CONF_CM_UNCACHED
248 mtc0 t0, CP0_CONFIG
249
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]250 /* Initialize $gp.
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]251 */
252 bal 1f
Wolfgang Denkc75eba32005-12-01 02:15:07 +0100[diff] [blame]253 nop
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]254 .word _gp
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]2551:
Shinya Kuribayashi16664f72007-11-17 20:05:26 +0900[diff] [blame]256 lw gp, 0(ra)
Wolfgang Denkc75eba32005-12-01 02:15:07 +0100[diff] [blame]257
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]258 /* Initialize any external memory.
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]259 */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]260 la t9, lowlevel_init
261 jalr t9
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]262 nop
263
264 /* Initialize caches...
265 */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]266 la t9, mips_cache_reset
267 jalr t9
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]268 nop
269
270 /* ... and enable them.
271 */
272 li t0, CONF_CM_CACHABLE_NONCOHERENT
273 mtc0 t0, CP0_CONFIG
274
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]275 /* Set up temporary stack.
276 */
Shinya Kuribayashie1390802008-03-25 11:39:29 +0900[diff] [blame]277#ifdef CFG_INIT_RAM_LOCK_MIPS
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]278 li a0, CFG_INIT_SP_OFFSET
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]279 la t9, mips_cache_lock
280 jalr t9
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]281 nop
Shinya Kuribayashie1390802008-03-25 11:39:29 +0900[diff] [blame]282#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]283
284 li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
285 la sp, 0(t0)
286
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]287 la t9, board_init_f
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]288 jr t9
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]289 nop
290
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]291/*
292 * void relocate_code (addr_sp, gd, addr_moni)
293 *
294 * This "function" does not return, instead it continues in RAM
295 * after relocating the monitor code.
296 *
297 * a0 = addr_sp
298 * a1 = gd
299 * a2 = destination address
300 */
301 .globl relocate_code
302 .ent relocate_code
303relocate_code:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]304 move sp, a0 /* Set new stack pointer */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]305
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]306 li t0, CFG_MONITOR_BASE
307 la t3, in_ram
308 lw t2, -12(t3) /* t2 <-- uboot_end_data */
309 move t1, a2
310
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]311 /*
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]312 * Fix $gp:
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]313 *
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]314 * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]315 */
316 move t6, gp
317 sub gp, CFG_MONITOR_BASE
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]318 add gp, a2 /* gp now adjusted */
319 sub t6, gp, t6 /* t6 <-- relocation offset */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]320
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]321 /*
322 * t0 = source address
323 * t1 = target address
324 * t2 = source end address
325 */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]326 /* On the purple board we copy the code earlier in a special way
327 * in order to solve flash problems
328 */
329#ifndef CONFIG_PURPLE
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]3301:
331 lw t3, 0(t0)
332 sw t3, 0(t1)
333 addu t0, 4
334 ble t0, t2, 1b
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]335 addu t1, 4 /* delay slot */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]336#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]337
338 /* If caches were enabled, we would have to flush them here.
339 */
340
341 /* Jump to where we've relocated ourselves.
342 */
343 addi t0, a2, in_ram - _start
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]344 jr t0
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]345 nop
346
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]347 .word _gp
Vlad Lungu0f8c62a2008-05-05 14:04:00 +0300[diff] [blame]348 .word _GLOBAL_OFFSET_TABLE_
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]349 .word uboot_end_data
350 .word uboot_end
351 .word num_got_entries
352
353in_ram:
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]354 /*
355 * Now we want to update GOT.
356 *
357 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
358 * generated by GNU ld. Skip these reserved entries from relocation.
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]359 */
360 lw t3, -4(t0) /* t3 <-- num_got_entries */
Vlad Lungu0f8c62a2008-05-05 14:04:00 +0300[diff] [blame]361 lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
362 lw t5, -20(t0) /* t5 <-- _gp */
363 sub t4, t5 /* compute offset*/
364 add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]365 addi t4, t4, 8 /* Skipping first two entries. */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]366 li t2, 2
3671:
368 lw t1, 0(t4)
369 beqz t1, 2f
370 add t1, t6
371 sw t1, 0(t4)
3722:
373 addi t2, 1
374 blt t2, t3, 1b
375 addi t4, 4 /* delay slot */
376
377 /* Clear BSS.
378 */
379 lw t1, -12(t0) /* t1 <-- uboot_end_data */
380 lw t2, -8(t0) /* t2 <-- uboot_end */
381 add t1, t6 /* adjust pointers */
382 add t2, t6
383
384 sub t1, 4
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]3851:
386 addi t1, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]387 bltl t1, t2, 1b
388 sw zero, 0(t1) /* delay slot */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]389
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]390 move a0, a1
391 la t9, board_init_r
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]392 jr t9
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]393 move a1, a2 /* delay slot */
394
395 .end relocate_code
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]396
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]397 /* Exception handlers.
398 */
399romReserved:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]400 b romReserved
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]401
402romExcHandle:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]403 b romExcHandle