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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02002/*
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02004 */
5
6#include <common.h>
Marek Vasut38b92ca2021-01-19 00:58:33 +01007#include <clk.h>
Peng Fan994266b2017-08-09 13:09:33 +08008#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020010#include <malloc.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020011#include <spi.h>
Simon Glass401d1c42020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glass336d4612020-02-03 07:36:16 -070013#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060014#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060015#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090016#include <linux/errno.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020017#include <asm/io.h>
Stefano Babicd8e0ca82011-08-21 10:45:44 +020018#include <asm/gpio.h>
Stefano Babic86271112011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
20#include <asm/arch/clock.h>
Stefano Babic552a8482017-06-29 10:16:06 +020021#include <asm/mach-imx/spi.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020022
Peng Fan994266b2017-08-09 13:09:33 +080023DECLARE_GLOBAL_DATA_PTR;
24
Marek Vasut6cd4f482021-01-19 00:58:32 +010025/* MX35 and older is CSPI */
26#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
27#define MXC_CSPI
28struct cspi_regs {
29 u32 rxdata;
30 u32 txdata;
31 u32 ctrl;
32 u32 intr;
33 u32 dma;
34 u32 stat;
35 u32 period;
36 u32 test;
37};
38
39#define MXC_CSPICTRL_EN BIT(0)
40#define MXC_CSPICTRL_MODE BIT(1)
41#define MXC_CSPICTRL_XCH BIT(2)
42#define MXC_CSPICTRL_SMC BIT(3)
43#define MXC_CSPICTRL_POL BIT(4)
44#define MXC_CSPICTRL_PHA BIT(5)
45#define MXC_CSPICTRL_SSCTL BIT(6)
46#define MXC_CSPICTRL_SSPOL BIT(7)
47#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
48#define MXC_CSPICTRL_RXOVF BIT(6)
49#define MXC_CSPIPERIOD_32KHZ BIT(15)
50#define MAX_SPI_BYTES 4
51#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
52#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
53#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
54#define MXC_CSPICTRL_TC BIT(7)
55#define MXC_CSPICTRL_MAXBITS 0xfff
56#else /* MX31 */
57#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
58#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
59#define MXC_CSPICTRL_TC BIT(8)
60#define MXC_CSPICTRL_MAXBITS 0x1f
61#endif
62
63#else /* MX51 and newer is ECSPI */
64#define MXC_ECSPI
65struct cspi_regs {
66 u32 rxdata;
67 u32 txdata;
68 u32 ctrl;
69 u32 cfg;
70 u32 intr;
71 u32 dma;
72 u32 stat;
73 u32 period;
74};
75
76#define MXC_CSPICTRL_EN BIT(0)
77#define MXC_CSPICTRL_MODE BIT(1)
78#define MXC_CSPICTRL_XCH BIT(2)
79#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
80#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
81#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
82#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
83#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
84#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
85#define MXC_CSPICTRL_MAXBITS 0xfff
86#define MXC_CSPICTRL_TC BIT(7)
87#define MXC_CSPICTRL_RXOVF BIT(6)
88#define MXC_CSPIPERIOD_32KHZ BIT(15)
89#define MAX_SPI_BYTES 32
90
91/* Bit position inside CTRL register to be associated with SS */
92#define MXC_CSPICTRL_CHAN 18
93
94/* Bit position inside CON register to be associated with SS */
95#define MXC_CSPICON_PHA 0 /* SCLK phase control */
96#define MXC_CSPICON_POL 4 /* SCLK polarity */
97#define MXC_CSPICON_SSPOL 12 /* SS polarity */
98#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
99#endif
100
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200101#ifdef CONFIG_MX27
102/* i.MX27 has a completely wrong register layout and register definitions in the
103 * datasheet, the correct one is in the Freescale's Linux driver */
104
Helmut Raiger61a58a12011-06-15 01:45:45 +0000105#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200106"See linux mxc_spi driver from Freescale for details."
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200107#endif
108
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300109__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
110{
111 return -1;
112}
113
Stefano Babicc4ea1422010-07-06 17:05:06 +0200114#define OUT MXC_GPIO_DIRECTION_OUT
115
Stefano Babicac87c172011-01-19 22:46:33 +0000116#define reg_read readl
117#define reg_write(a, v) writel(v, a)
118
Heiko Schocherf659b572014-07-14 10:22:11 +0200119#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
120#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
121#endif
122
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200123#define MAX_CS_COUNT 4
124
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200125struct mxc_spi_slave {
126 struct spi_slave slave;
127 unsigned long base;
128 u32 ctrl_reg;
Eric Nelson08c61a52012-01-31 07:52:03 +0000129#if defined(MXC_ECSPI)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200130 u32 cfg_reg;
131#endif
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100132 int gpio;
Stefano Babicc4ea1422010-07-06 17:05:06 +0200133 int ss_pol;
Markus Niebel027a9a02014-10-23 16:09:39 +0200134 unsigned int max_hz;
135 unsigned int mode;
Peng Fan994266b2017-08-09 13:09:33 +0800136 struct gpio_desc ss;
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200137 struct gpio_desc cs_gpios[MAX_CS_COUNT];
138 struct udevice *dev;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200139};
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200140
141static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
142{
143 return container_of(slave, struct mxc_spi_slave, slave);
144}
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200145
Peng Fan994266b2017-08-09 13:09:33 +0800146static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200147{
Lukasz Majewski56c40462020-06-04 23:11:53 +0800148#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200149 struct udevice *dev = mxcs->dev;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700150 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200151
152 u32 cs = slave_plat->cs;
153
154 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
155 return;
156
157 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
158#else
159 if (mxcs->gpio > 0)
160 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
161#endif
Stefano Babicd205ddc2010-04-04 22:43:38 +0200162}
163
Peng Fan994266b2017-08-09 13:09:33 +0800164static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200165{
Lukasz Majewski56c40462020-06-04 23:11:53 +0800166#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200167 struct udevice *dev = mxcs->dev;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700168 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200169
170 u32 cs = slave_plat->cs;
171
172 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
173 return;
174
175 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
176#else
177 if (mxcs->gpio > 0)
178 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
179#endif
Stefano Babicd205ddc2010-04-04 22:43:38 +0200180}
181
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000182u32 get_cspi_div(u32 div)
183{
184 int i;
185
186 for (i = 0; i < 8; i++) {
187 if (div <= (4 << i))
188 return i;
189 }
190 return i;
191}
192
Eric Nelson08c61a52012-01-31 07:52:03 +0000193#ifdef MXC_CSPI
Markus Niebel027a9a02014-10-23 16:09:39 +0200194static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicc9d59c72011-01-19 22:46:30 +0000195{
196 unsigned int ctrl_reg;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000197 u32 clk_src;
198 u32 div;
Markus Niebel027a9a02014-10-23 16:09:39 +0200199 unsigned int max_hz = mxcs->max_hz;
200 unsigned int mode = mxcs->mode;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000201
202 clk_src = mxc_get_clock(MXC_CSPI_CLK);
203
Benoît Thébaudeaucd200402012-08-10 08:51:50 +0000204 div = DIV_ROUND_UP(clk_src, max_hz);
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000205 div = get_cspi_div(div);
206
207 debug("clk %d Hz, div %d, real clk %d Hz\n",
208 max_hz, div, clk_src / (4 << div));
Stefano Babicc9d59c72011-01-19 22:46:30 +0000209
210 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
211 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000212 MXC_CSPICTRL_DATARATE(div) |
Stefano Babicc9d59c72011-01-19 22:46:30 +0000213 MXC_CSPICTRL_EN |
214#ifdef CONFIG_MX35
215 MXC_CSPICTRL_SSCTL |
216#endif
217 MXC_CSPICTRL_MODE;
218
219 if (mode & SPI_CPHA)
220 ctrl_reg |= MXC_CSPICTRL_PHA;
221 if (mode & SPI_CPOL)
222 ctrl_reg |= MXC_CSPICTRL_POL;
223 if (mode & SPI_CS_HIGH)
224 ctrl_reg |= MXC_CSPICTRL_SSPOL;
225 mxcs->ctrl_reg = ctrl_reg;
226
227 return 0;
228}
229#endif
230
Eric Nelson08c61a52012-01-31 07:52:03 +0000231#ifdef MXC_ECSPI
Markus Niebel027a9a02014-10-23 16:09:39 +0200232static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200233{
234 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
Dirk Behme9a309032013-05-11 07:25:54 +0200235 s32 reg_ctrl, reg_config;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100236 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
237 u32 pre_div = 0, post_div = 0;
Stefano Babicac87c172011-01-19 22:46:33 +0000238 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Markus Niebel027a9a02014-10-23 16:09:39 +0200239 unsigned int max_hz = mxcs->max_hz;
240 unsigned int mode = mxcs->mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200241
Fabio Estevam0f1411b2013-04-09 13:06:25 +0000242 /*
243 * Reset SPI and set all CSs to master mode, if toggling
244 * between slave and master mode we might see a glitch
245 * on the clock line
246 */
247 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
248 reg_write(&regs->ctrl, reg_ctrl);
249 reg_ctrl |= MXC_CSPICTRL_EN;
250 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200251
Stefano Babicd205ddc2010-04-04 22:43:38 +0200252 if (clk_src > max_hz) {
Dirk Behme9a309032013-05-11 07:25:54 +0200253 pre_div = (clk_src - 1) / max_hz;
254 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
255 post_div = fls(pre_div);
256 if (post_div > 4) {
257 post_div -= 4;
258 if (post_div >= 16) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200259 printf("Error: no divider for the freq: %d\n",
260 max_hz);
261 return -1;
262 }
Dirk Behme9a309032013-05-11 07:25:54 +0200263 pre_div >>= post_div;
264 } else {
265 post_div = 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200266 }
267 }
268
269 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
270 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
271 MXC_CSPICTRL_SELCHAN(cs);
272 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
273 MXC_CSPICTRL_PREDIV(pre_div);
274 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
275 MXC_CSPICTRL_POSTDIV(post_div);
276
Stefano Babicd205ddc2010-04-04 22:43:38 +0200277 if (mode & SPI_CS_HIGH)
278 ss_pol = 1;
279
Markus Niebel5d584cc2014-02-17 17:33:17 +0100280 if (mode & SPI_CPOL) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200281 sclkpol = 1;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100282 sclkctl = 1;
283 }
Stefano Babicd205ddc2010-04-04 22:43:38 +0200284
285 if (mode & SPI_CPHA)
286 sclkpha = 1;
287
Stefano Babicac87c172011-01-19 22:46:33 +0000288 reg_config = reg_read(&regs->cfg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200289
290 /*
291 * Configuration register setup
Stefano Babicc9d59c72011-01-19 22:46:30 +0000292 * The MX51 supports different setup for each SS
Stefano Babicd205ddc2010-04-04 22:43:38 +0200293 */
294 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
295 (ss_pol << (cs + MXC_CSPICON_SSPOL));
296 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
297 (sclkpol << (cs + MXC_CSPICON_POL));
Markus Niebel5d584cc2014-02-17 17:33:17 +0100298 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
299 (sclkctl << (cs + MXC_CSPICON_CTL));
Stefano Babicd205ddc2010-04-04 22:43:38 +0200300 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
301 (sclkpha << (cs + MXC_CSPICON_PHA));
302
303 debug("reg_ctrl = 0x%x\n", reg_ctrl);
Stefano Babicac87c172011-01-19 22:46:33 +0000304 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200305 debug("reg_config = 0x%x\n", reg_config);
Stefano Babicac87c172011-01-19 22:46:33 +0000306 reg_write(&regs->cfg, reg_config);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200307
308 /* save config register and control register */
309 mxcs->ctrl_reg = reg_ctrl;
310 mxcs->cfg_reg = reg_config;
311
312 /* clear interrupt reg */
Stefano Babicac87c172011-01-19 22:46:33 +0000313 reg_write(&regs->intr, 0);
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200315
316 return 0;
317}
318#endif
319
Peng Fan994266b2017-08-09 13:09:33 +0800320int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
Stefano Babic2f721d12010-08-20 12:05:03 +0200321 const u8 *dout, u8 *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200322{
Axel Lin9675fed2013-06-14 21:13:32 +0800323 int nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200324 u32 data, cnt, i;
Stefano Babicac87c172011-01-19 22:46:33 +0000325 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Heiko Schocherf659b572014-07-14 10:22:11 +0200326 u32 ts;
327 int status;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200328
Ye Li65a106e2019-01-04 09:26:00 +0000329 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
330 __func__, bitlen, (ulong)dout, (ulong)din);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200331
332 mxcs->ctrl_reg = (mxcs->ctrl_reg &
333 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100334 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
335
Stefano Babicac87c172011-01-19 22:46:33 +0000336 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
Eric Nelson08c61a52012-01-31 07:52:03 +0000337#ifdef MXC_ECSPI
Stefano Babicac87c172011-01-19 22:46:33 +0000338 reg_write(&regs->cfg, mxcs->cfg_reg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200339#endif
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200340
Stefano Babicd205ddc2010-04-04 22:43:38 +0200341 /* Clear interrupt register */
Stefano Babicac87c172011-01-19 22:46:33 +0000342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100343
Stefano Babic2f721d12010-08-20 12:05:03 +0200344 /*
345 * The SPI controller works only with words,
346 * check if less than a word is sent.
347 * Access to the FIFO is only 32 bit
348 */
349 if (bitlen % 32) {
350 data = 0;
351 cnt = (bitlen % 32) / 8;
352 if (dout) {
353 for (i = 0; i < cnt; i++) {
354 data = (data << 8) | (*dout++ & 0xFF);
355 }
356 }
357 debug("Sending SPI 0x%x\n", data);
358
Stefano Babicac87c172011-01-19 22:46:33 +0000359 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200360 nbytes -= cnt;
361 }
362
363 data = 0;
364
365 while (nbytes > 0) {
366 data = 0;
367 if (dout) {
368 /* Buffer is not 32-bit aligned */
369 if ((unsigned long)dout & 0x03) {
370 data = 0;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000371 for (i = 0; i < 4; i++)
Stefano Babic2f721d12010-08-20 12:05:03 +0200372 data = (data << 8) | (*dout++ & 0xFF);
Stefano Babic2f721d12010-08-20 12:05:03 +0200373 } else {
374 data = *(u32 *)dout;
375 data = cpu_to_be32(data);
Timo Herbrecher6d5ce1b2013-10-16 00:05:09 +0530376 dout += 4;
Stefano Babic2f721d12010-08-20 12:05:03 +0200377 }
Stefano Babic2f721d12010-08-20 12:05:03 +0200378 }
379 debug("Sending SPI 0x%x\n", data);
Stefano Babicac87c172011-01-19 22:46:33 +0000380 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200381 nbytes -= 4;
382 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200383
Stefano Babicd205ddc2010-04-04 22:43:38 +0200384 /* FIFO is written, now starts the transfer setting the XCH bit */
Stefano Babicac87c172011-01-19 22:46:33 +0000385 reg_write(&regs->ctrl, mxcs->ctrl_reg |
Stefano Babicd205ddc2010-04-04 22:43:38 +0200386 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200387
Heiko Schocherf659b572014-07-14 10:22:11 +0200388 ts = get_timer(0);
389 status = reg_read(&regs->stat);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200390 /* Wait until the TC (Transfer completed) bit is set */
Heiko Schocherf659b572014-07-14 10:22:11 +0200391 while ((status & MXC_CSPICTRL_TC) == 0) {
392 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
393 printf("spi_xchg_single: Timeout!\n");
394 return -1;
395 }
396 status = reg_read(&regs->stat);
397 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200398
Stefano Babicd205ddc2010-04-04 22:43:38 +0200399 /* Transfer completed, clear any pending request */
Stefano Babicac87c172011-01-19 22:46:33 +0000400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100401
Axel Lin9675fed2013-06-14 21:13:32 +0800402 nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200403
Stefano Babic2f721d12010-08-20 12:05:03 +0200404 cnt = nbytes % 32;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200405
Stefano Babic2f721d12010-08-20 12:05:03 +0200406 if (bitlen % 32) {
Stefano Babicac87c172011-01-19 22:46:33 +0000407 data = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200408 cnt = (bitlen % 32) / 8;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000409 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200410 debug("SPI Rx unaligned: 0x%x\n", data);
411 if (din) {
Anatolij Gustschindff01092011-01-20 07:53:06 +0000412 memcpy(din, &data, cnt);
413 din += cnt;
Stefano Babic2f721d12010-08-20 12:05:03 +0200414 }
415 nbytes -= cnt;
416 }
417
418 while (nbytes > 0) {
419 u32 tmp;
Stefano Babicac87c172011-01-19 22:46:33 +0000420 tmp = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200421 data = cpu_to_be32(tmp);
422 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
Masahiro Yamadab4141192014-11-07 03:03:31 +0900423 cnt = min_t(u32, nbytes, sizeof(data));
Stefano Babic2f721d12010-08-20 12:05:03 +0200424 if (din) {
425 memcpy(din, &data, cnt);
426 din += cnt;
427 }
428 nbytes -= cnt;
429 }
430
431 return 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200432
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200433}
434
Peng Fan994266b2017-08-09 13:09:33 +0800435static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
436 unsigned int bitlen, const void *dout,
437 void *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200438{
Axel Lin9675fed2013-06-14 21:13:32 +0800439 int n_bytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200440 int n_bits;
441 int ret;
442 u32 blk_size;
443 u8 *p_outbuf = (u8 *)dout;
444 u8 *p_inbuf = (u8 *)din;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200445
Peng Fan994266b2017-08-09 13:09:33 +0800446 if (!mxcs)
447 return -EINVAL;
Stefano Babic2f721d12010-08-20 12:05:03 +0200448
449 if (flags & SPI_XFER_BEGIN)
Peng Fan994266b2017-08-09 13:09:33 +0800450 mxc_spi_cs_activate(mxcs);
Stefano Babic2f721d12010-08-20 12:05:03 +0200451
452 while (n_bytes > 0) {
Stefano Babic2f721d12010-08-20 12:05:03 +0200453 if (n_bytes < MAX_SPI_BYTES)
454 blk_size = n_bytes;
455 else
456 blk_size = MAX_SPI_BYTES;
457
458 n_bits = blk_size * 8;
459
Peng Fan994266b2017-08-09 13:09:33 +0800460 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
Stefano Babic2f721d12010-08-20 12:05:03 +0200461
462 if (ret)
463 return ret;
464 if (dout)
465 p_outbuf += blk_size;
466 if (din)
467 p_inbuf += blk_size;
468 n_bytes -= blk_size;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200469 }
470
Stefano Babic2f721d12010-08-20 12:05:03 +0200471 if (flags & SPI_XFER_END) {
Peng Fan994266b2017-08-09 13:09:33 +0800472 mxc_spi_cs_deactivate(mxcs);
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100473 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200474
475 return 0;
476}
477
Peng Fan994266b2017-08-09 13:09:33 +0800478static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
479{
480 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
481 int ret;
482
483 reg_write(&regs->rxdata, 1);
484 udelay(1);
485 ret = spi_cfg_mxc(mxcs, cs);
486 if (ret) {
487 printf("mxc_spi: cannot setup SPI controller\n");
488 return ret;
489 }
490 reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
491 reg_write(&regs->intr, 0);
492
493 return 0;
494}
495
Lukasz Majewski56c40462020-06-04 23:11:53 +0800496#if !CONFIG_IS_ENABLED(DM_SPI)
Peng Fan994266b2017-08-09 13:09:33 +0800497int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
498 void *din, unsigned long flags)
499{
500 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
501
502 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
503}
504
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300505/*
506 * Some SPI devices require active chip-select over multiple
507 * transactions, we achieve this using a GPIO. Still, the SPI
508 * controller has to be configured to use one of its own chipselects.
509 * To use this feature you have to implement board_spi_cs_gpio() to assign
510 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
511 * You must use some unused on this SPI controller cs between 0 and 3.
512 */
513static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
514 unsigned int bus, unsigned int cs)
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100515{
516 int ret;
517
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300518 mxcs->gpio = board_spi_cs_gpio(bus, cs);
519 if (mxcs->gpio == -1)
520 return 0;
521
Peng Fan994266b2017-08-09 13:09:33 +0800522 gpio_request(mxcs->gpio, "spi-cs");
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300523 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
524 if (ret) {
525 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
526 return -EINVAL;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100527 }
528
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300529 return 0;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100530}
531
Peng Fan994266b2017-08-09 13:09:33 +0800532static unsigned long spi_bases[] = {
533 MXC_SPI_BASE_ADDRESSES
534};
535
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200536struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
537 unsigned int max_hz, unsigned int mode)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200538{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200539 struct mxc_spi_slave *mxcs;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100540 int ret;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200541
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100542 if (bus >= ARRAY_SIZE(spi_bases))
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200543 return NULL;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200544
Markus Niebel027a9a02014-10-23 16:09:39 +0200545 if (max_hz == 0) {
546 printf("Error: desired clock is 0\n");
547 return NULL;
548 }
549
Simon Glassd3504fe2013-03-18 19:23:40 +0000550 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
Stefano Babic2f721d12010-08-20 12:05:03 +0200551 if (!mxcs) {
552 puts("mxc_spi: SPI Slave not allocated !\n");
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100553 return NULL;
Stefano Babic2f721d12010-08-20 12:05:03 +0200554 }
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100555
Fabio Estevamde5bf022012-11-15 11:23:23 +0000556 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
557
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300558 ret = setup_cs_gpio(mxcs, bus, cs);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100559 if (ret < 0) {
560 free(mxcs);
561 return NULL;
562 }
563
Stefano Babicd205ddc2010-04-04 22:43:38 +0200564 mxcs->base = spi_bases[bus];
Markus Niebel027a9a02014-10-23 16:09:39 +0200565 mxcs->max_hz = max_hz;
566 mxcs->mode = mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200567
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200568 return &mxcs->slave;
569}
570
571void spi_free_slave(struct spi_slave *slave)
572{
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100573 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
574
575 free(mxcs);
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200576}
577
578int spi_claim_bus(struct spi_slave *slave)
579{
580 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
581
Peng Fan994266b2017-08-09 13:09:33 +0800582 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200583}
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200584
585void spi_release_bus(struct spi_slave *slave)
586{
587 /* TODO: Shut the controller down */
588}
Peng Fan994266b2017-08-09 13:09:33 +0800589#else
590
591static int mxc_spi_probe(struct udevice *bus)
592{
Simon Glassc69cda22020-12-03 16:55:20 -0700593 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
Peng Fan994266b2017-08-09 13:09:33 +0800594 int node = dev_of_offset(bus);
595 const void *blob = gd->fdt_blob;
596 int ret;
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200597 int i;
Peng Fan994266b2017-08-09 13:09:33 +0800598
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200599 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
600 ARRAY_SIZE(mxcs->cs_gpios), 0);
601 if (ret < 0) {
602 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
603 return ret;
604 }
605
606 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
607 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
608 continue;
609
610 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
611 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
612 if (ret) {
613 dev_err(bus, "Setting cs %d error\n", i);
614 return ret;
615 }
Peng Fan994266b2017-08-09 13:09:33 +0800616 }
617
Masahiro Yamada25484932020-07-17 14:36:48 +0900618 mxcs->base = dev_read_addr(bus);
Heiko Schocher2b849e12019-05-26 12:15:46 +0200619 if (mxcs->base == FDT_ADDR_T_NONE)
Peng Fan994266b2017-08-09 13:09:33 +0800620 return -ENODEV;
621
Marek Vasut38b92ca2021-01-19 00:58:33 +0100622#if CONFIG_IS_ENABLED(CLK)
623 struct clk clk;
624 ret = clk_get_by_index(bus, 0, &clk);
625 if (ret)
626 return ret;
627
628 clk_enable(&clk);
629
630 mxcs->max_hz = clk_get_rate(&clk);
631#else
Peng Fan994266b2017-08-09 13:09:33 +0800632 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
633 20000000);
Marek Vasut38b92ca2021-01-19 00:58:33 +0100634#endif
Peng Fan994266b2017-08-09 13:09:33 +0800635
636 return 0;
637}
638
639static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
640 const void *dout, void *din, unsigned long flags)
641{
Simon Glassc69cda22020-12-03 16:55:20 -0700642 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
Peng Fan994266b2017-08-09 13:09:33 +0800643
644
645 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
646}
647
648static int mxc_spi_claim_bus(struct udevice *dev)
649{
Simon Glassc69cda22020-12-03 16:55:20 -0700650 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
Simon Glass8a8d24b2020-12-03 16:55:23 -0700651 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Peng Fan994266b2017-08-09 13:09:33 +0800652
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200653 mxcs->dev = dev;
654
Peng Fan994266b2017-08-09 13:09:33 +0800655 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
656}
657
658static int mxc_spi_release_bus(struct udevice *dev)
659{
660 return 0;
661}
662
663static int mxc_spi_set_speed(struct udevice *bus, uint speed)
664{
Marek Vasutc1d264e2021-02-03 17:53:57 +0100665 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
666
667 mxcs->max_hz = speed;
668
Peng Fan994266b2017-08-09 13:09:33 +0800669 return 0;
670}
671
672static int mxc_spi_set_mode(struct udevice *bus, uint mode)
673{
Simon Glassc69cda22020-12-03 16:55:20 -0700674 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
Peng Fan994266b2017-08-09 13:09:33 +0800675
676 mxcs->mode = mode;
677 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
678
679 return 0;
680}
681
682static const struct dm_spi_ops mxc_spi_ops = {
683 .claim_bus = mxc_spi_claim_bus,
684 .release_bus = mxc_spi_release_bus,
685 .xfer = mxc_spi_xfer,
686 .set_speed = mxc_spi_set_speed,
687 .set_mode = mxc_spi_set_mode,
688};
689
690static const struct udevice_id mxc_spi_ids[] = {
691 { .compatible = "fsl,imx51-ecspi" },
692 { }
693};
694
695U_BOOT_DRIVER(mxc_spi) = {
696 .name = "mxc_spi",
697 .id = UCLASS_SPI,
698 .of_match = mxc_spi_ids,
699 .ops = &mxc_spi_ops,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700700 .plat_auto = sizeof(struct mxc_spi_slave),
Peng Fan994266b2017-08-09 13:09:33 +0800701 .probe = mxc_spi_probe,
702};
703#endif