blob: d09cd477424e1348c03c9cd70573925709e7daf5 [file] [log] [blame]
Luka Kovacicdf9ebbe2020-05-26 20:17:50 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CRS305-1G-4S board
4 *
5 * Copyright (C) 2016 Allied Telesis Labs
6 * Copyright (C) 2020 Sartura Ltd.
7 *
8 * Based on armada-xp-db.dts
9 *
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
18 */
19
20/dts-v1/;
21#include "armada-xp-98dx3236.dtsi"
Luka Kovacicdf9ebbe2020-05-26 20:17:50 +020022
23/ {
24 model = "CRS305-1G-4S+";
25 compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 bootargs = "console=ttyS0,115200 earlyprintk";
30 };
31
32 aliases {
33 spi0 = &spi0;
34 };
35
36 memory {
37 device_type = "memory";
38 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
39 };
40};
41
42&L2 {
43 arm,parity-enable;
44 marvell,ecc-enable;
45};
46
47&devbus_bootcs {
48 status = "okay";
49
50 /* Device Bus parameters are required */
51
52 /* Read parameters */
53 devbus,bus-width = <16>;
54 devbus,turn-off-ps = <60000>;
55 devbus,badr-skew-ps = <0>;
56 devbus,acc-first-ps = <124000>;
57 devbus,acc-next-ps = <248000>;
58 devbus,rd-setup-ps = <0>;
59 devbus,rd-hold-ps = <0>;
60
61 /* Write parameters */
62 devbus,sync-enable = <0>;
63 devbus,wr-high-ps = <60000>;
64 devbus,wr-low-ps = <60000>;
65 devbus,ale-wr-ps = <60000>;
66};
67
68&uart0 {
69 status = "okay";
70};
71
72&uart1 {
73 status = "okay";
74};
75
76&i2c0 {
77 clock-frequency = <100000>;
78 status = "okay";
79};
80
81&usb0 {
82 status = "okay";
83};
84
85&spi0 {
86 status = "okay";
87
88 spi-flash@0 {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "spi-flash", "jedec,spi-nor";
92 reg = <0>; /* Chip select 0 */
93 spi-max-frequency = <108000000>;
94 m25p,fast-read;
95
96 partition@u-boot {
Luka Kovacic14133652020-07-23 10:56:40 +020097 reg = <0x00000000 0x001f0000>;
Luka Kovacicdf9ebbe2020-05-26 20:17:50 +020098 label = "u-boot";
99 };
100 partition@u-boot-env {
Luka Kovacic14133652020-07-23 10:56:40 +0200101 reg = <0x001f0000 0x00010000>;
Luka Kovacicdf9ebbe2020-05-26 20:17:50 +0200102 label = "u-boot-env";
103 };
Luka Kovacic14133652020-07-23 10:56:40 +0200104 partition@ubi1 {
105 reg = <0x00200000 0x00e00000>;
106 label = "ubi1";
Luka Kovacicdf9ebbe2020-05-26 20:17:50 +0200107 };
108
109 };
110};