blob: 41752c0b6af362b2442680e1a2c3141c0ecd6250 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiew777d1ab2008-01-15 14:00:25 -06002/*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew777d1ab2008-01-15 14:00:25 -06008 */
9
10#include <common.h>
Simon Glass7b51b572019-08-01 09:46:52 -060011#include <env.h>
Alex Kiernan9925f1d2018-04-01 09:22:38 +000012#include <environment.h>
TsiChungLiew777d1ab2008-01-15 14:00:25 -060013#include <malloc.h>
14#include <command.h>
15#include <config.h>
16#include <net.h>
17#include <miiphy.h>
18
TsiChungLiew777d1ab2008-01-15 14:00:25 -060019#undef ET_DEBUG
20#undef MII_DEBUG
21
22/* Ethernet Transmit and Receive Buffers */
23#define DBUF_LENGTH 1520
24#define PKT_MAXBUF_SIZE 1518
25#define PKT_MINBUF_SIZE 64
26#define PKT_MAXBLR_SIZE 1536
27#define LAST_PKTBUFSRX PKTBUFSRX - 1
28#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
29#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
30#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
31
32/* RxBD bits definitions */
33#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
34 BD_ENET_RX_OV | BD_ENET_RX_TR)
35
TsiChungLiew777d1ab2008-01-15 14:00:25 -060036#include <asm/immap.h>
37#include <asm/fsl_mcdmafec.h>
38
39#include "MCD_dma.h"
40
TsiChungLiew777d1ab2008-01-15 14:00:25 -060041struct fec_info_dma fec_info[] = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#ifdef CONFIG_SYS_FEC0_IOBASE
TsiChungLiew777d1ab2008-01-15 14:00:25 -060043 {
44 0, /* index */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 CONFIG_SYS_FEC0_IOBASE, /* io base */
46 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
47 CONFIG_SYS_FEC0_MIIBASE, /* mii base */
TsiChungLiew777d1ab2008-01-15 14:00:25 -060048 -1, /* phy_addr */
49 0, /* duplex and speed */
50 0, /* phy name */
51 0, /* phyname init */
52 0, /* RX BD */
53 0, /* TX BD */
54 0, /* rx Index */
55 0, /* tx Index */
56 0, /* tx buffer */
57 0, /* initialized flag */
58 (struct fec_info_dma *)-1, /* next */
59 FEC0_RX_TASK, /* rxTask */
60 FEC0_TX_TASK, /* txTask */
61 FEC0_RX_PRIORITY, /* rxPri */
62 FEC0_TX_PRIORITY, /* txPri */
63 FEC0_RX_INIT, /* rxInit */
64 FEC0_TX_INIT, /* txInit */
65 0, /* usedTbdIndex */
66 0, /* cleanTbdNum */
67 },
68#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#ifdef CONFIG_SYS_FEC1_IOBASE
TsiChungLiew777d1ab2008-01-15 14:00:25 -060070 {
71 1, /* index */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 CONFIG_SYS_FEC1_IOBASE, /* io base */
73 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
74 CONFIG_SYS_FEC1_MIIBASE, /* mii base */
TsiChungLiew777d1ab2008-01-15 14:00:25 -060075 -1, /* phy_addr */
76 0, /* duplex and speed */
77 0, /* phy name */
78 0, /* phy name init */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#ifdef CONFIG_SYS_DMA_USE_INTSRAM
TsiChung Liew429be272008-08-21 23:55:11 +000080 (cbd_t *)DBUF_LENGTH, /* RX BD */
TsiChung Liewf32f7fe2008-04-30 12:11:19 -050081#else
TsiChungLiew777d1ab2008-01-15 14:00:25 -060082 0, /* RX BD */
TsiChung Liewf32f7fe2008-04-30 12:11:19 -050083#endif
TsiChungLiew777d1ab2008-01-15 14:00:25 -060084 0, /* TX BD */
85 0, /* rx Index */
86 0, /* tx Index */
87 0, /* tx buffer */
88 0, /* initialized flag */
89 (struct fec_info_dma *)-1, /* next */
90 FEC1_RX_TASK, /* rxTask */
91 FEC1_TX_TASK, /* txTask */
92 FEC1_RX_PRIORITY, /* rxPri */
93 FEC1_TX_PRIORITY, /* txPri */
94 FEC1_RX_INIT, /* rxInit */
95 FEC1_TX_INIT, /* txInit */
96 0, /* usedTbdIndex */
97 0, /* cleanTbdNum */
98 }
99#endif
100};
101
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000102static int fec_send(struct eth_device *dev, void *packet, int length);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600103static int fec_recv(struct eth_device *dev);
104static int fec_init(struct eth_device *dev, bd_t * bd);
105static void fec_halt(struct eth_device *dev);
106
107#ifdef ET_DEBUG
108static void dbg_fec_regs(struct eth_device *dev)
109{
110 struct fec_info_dma *info = dev->priv;
111 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
112
113 printf("=====\n");
114 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
115 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
116 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
117 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
118 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
119 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
120 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
121 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
122 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
123 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
124 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
125 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
126 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
127 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
128 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
129 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
130 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
131 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
132 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
133 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
134 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
135 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
136 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
137 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
138 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
139 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
140 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
141 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
142 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
143 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
144 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
145 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
146 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
147 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
148 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
149}
150#endif
151
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500152static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
153 int dup_spd)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600154{
155 if ((dup_spd >> 16) == FULL) {
156 /* Set maximum frame length */
157 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
158 FEC_RCR_PROM | 0x100;
159 fecp->tcr = FEC_TCR_FDEN;
160 } else {
161 /* Half duplex mode */
162 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
163 FEC_RCR_MII_MODE | FEC_RCR_DRT;
164 fecp->tcr &= ~FEC_TCR_FDEN;
165 }
166
167 if ((dup_spd & 0xFFFF) == _100BASET) {
168#ifdef MII_DEBUG
169 printf("100Mbps\n");
170#endif
171 bd->bi_ethspeed = 100;
172 } else {
173#ifdef MII_DEBUG
174 printf("10Mbps\n");
175#endif
176 bd->bi_ethspeed = 10;
177 }
178}
179
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000180static int fec_send(struct eth_device *dev, void *packet, int length)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600181{
182 struct fec_info_dma *info = dev->priv;
183 cbd_t *pTbd, *pUsedTbd;
184 u16 phyStatus;
185
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500186 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600187
188 /* process all the consumed TBDs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600190 pUsedTbd = &info->txbd[info->usedTbdIdx];
191 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
192#ifdef ET_DEBUG
193 printf("Cannot clean TBD %d, in use\n",
194 info->cleanTbdNum);
195#endif
196 return 0;
197 }
198
199 /* clean this buffer descriptor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200 if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600201 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
202 else
203 pUsedTbd->cbd_sc = 0;
204
205 /* update some indeces for a correct handling of the TBD ring */
206 info->cleanTbdNum++;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600208 }
209
210 /* Check for valid length of data. */
211 if ((length > 1500) || (length <= 0)) {
212 return -1;
213 }
214
215 /* Check the number of vacant TxBDs. */
216 if (info->cleanTbdNum < 1) {
217 printf("No available TxBDs ...\n");
218 return -1;
219 }
220
221 /* Get the first TxBD to send the mac header */
222 pTbd = &info->txbd[info->txIdx];
223 pTbd->cbd_datlen = length;
224 pTbd->cbd_bufaddr = (u32) packet;
225 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226 info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600227
228 /* Enable DMA transmit task */
229 MCD_continDma(info->txTask);
230
231 info->cleanTbdNum -= 1;
232
233 /* wait until frame is sent . */
234 while (pTbd->cbd_sc & BD_ENET_TX_READY) {
235 udelay(10);
236 }
237
238 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
239}
240
241static int fec_recv(struct eth_device *dev)
242{
243 struct fec_info_dma *info = dev->priv;
244 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
245
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500246 cbd_t *prbd = &info->rxbd[info->rxIdx];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600247 u32 ievent;
248 int frame_length, len = 0;
249
250 /* Check if any critical events have happened */
251 ievent = fecp->eir;
252 if (ievent != 0) {
253 fecp->eir = ievent;
254
255 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
256 printf("fec_recv: error\n");
257 fec_halt(dev);
258 fec_init(dev, NULL);
259 return 0;
260 }
261
262 if (ievent & FEC_EIR_HBERR) {
263 /* Heartbeat error */
264 fecp->tcr |= FEC_TCR_GTS;
265 }
266
267 if (ievent & FEC_EIR_GRA) {
268 /* Graceful stop complete */
269 if (fecp->tcr & FEC_TCR_GTS) {
270 printf("fec_recv: tcr_gts\n");
271 fec_halt(dev);
272 fecp->tcr &= ~FEC_TCR_GTS;
273 fec_init(dev, NULL);
274 }
275 }
276 }
277
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500278 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
279 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
280 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
281 ((prbd->cbd_datlen - 4) > 14)) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600282
283 /* Get buffer address and size */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500284 frame_length = prbd->cbd_datlen - 4;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600285
286 /* Fill the buffer and pass it to upper layers */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500287 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
288 frame_length);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600289 len = frame_length;
290 }
291
292 /* Reset buffer descriptor as empty */
293 if ((info->rxIdx) == (PKTBUFSRX - 1))
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500294 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600295 else
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500296 prbd->cbd_sc = BD_ENET_RX_EMPTY;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600297
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500298 prbd->cbd_datlen = PKTSIZE_ALIGN;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600299
300 /* Now, we have an empty RxBD, restart the DMA receive task */
301 MCD_continDma(info->rxTask);
302
303 /* Increment BD count */
304 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
305 }
306
307 return len;
308}
309
310static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
311{
312 u8 currByte; /* byte for which to compute the CRC */
313 int byte; /* loop - counter */
314 int bit; /* loop - counter */
315 u32 crc = 0xffffffff; /* initial value */
316
317 for (byte = 0; byte < 6; byte++) {
318 currByte = mac[byte];
319 for (bit = 0; bit < 8; bit++) {
320 if ((currByte & 0x01) ^ (crc & 0x01)) {
321 crc >>= 1;
322 crc = crc ^ 0xedb88320;
323 } else {
324 crc >>= 1;
325 }
326 currByte >>= 1;
327 }
328 }
329
330 crc = crc >> 26;
331
332 /* Set individual hash table register */
333 if (crc >= 32) {
334 fecp->ialr = (1 << (crc - 32));
335 fecp->iaur = 0;
336 } else {
337 fecp->ialr = 0;
338 fecp->iaur = (1 << crc);
339 }
340
341 /* Set physical address */
342 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
343 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
344
345 /* Clear multicast address hash table */
346 fecp->gaur = 0;
347 fecp->galr = 0;
348}
349
350static int fec_init(struct eth_device *dev, bd_t * bd)
351{
352 struct fec_info_dma *info = dev->priv;
353 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
354 int i;
Mike Frysingerd3f87142009-02-11 19:01:26 -0500355 uchar enetaddr[6];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600356
357#ifdef ET_DEBUG
358 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
359#endif
360
361 fecpin_setclear(dev, 1);
362
363 fec_halt(dev);
364
365#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366 defined (CONFIG_SYS_DISCOVER_PHY)
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600367
368 mii_init();
369
370 set_fec_duplex_speed(fecp, bd, info->dup_spd);
371#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600373 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600375#endif /* CONFIG_CMD_MII || CONFIG_MII */
376
377 /* We use strictly polling mode only */
378 fecp->eimr = 0;
379
380 /* Clear any pending interrupt */
381 fecp->eir = 0xffffffff;
382
383 /* Set station address */
Mike Frysingerd3f87142009-02-11 19:01:26 -0500384 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
Simon Glass35affd72017-08-03 12:22:14 -0600385 eth_env_get_enetaddr("ethaddr", enetaddr);
Mike Frysingerd3f87142009-02-11 19:01:26 -0500386 else
Simon Glass35affd72017-08-03 12:22:14 -0600387 eth_env_get_enetaddr("eth1addr", enetaddr);
Mike Frysingerd3f87142009-02-11 19:01:26 -0500388 fec_set_hwaddr(fecp, enetaddr);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600389
390 /* Set Opcode/Pause Duration Register */
391 fecp->opd = 0x00010020;
392
Heinrich Schuchardte4691562017-08-29 18:44:37 +0200393 /* Setup Buffers and Buffer Descriptors */
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600394 info->rxIdx = 0;
395 info->txIdx = 0;
396
397 /* Setup Receiver Buffer Descriptors (13.14.24.18)
398 * Settings: Empty, Wrap */
399 for (i = 0; i < PKTBUFSRX; i++) {
400 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
401 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500402 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600403 }
404 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
405
406 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
407 * Settings: Last, Tx CRC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600409 info->txbd[i].cbd_sc = 0;
410 info->txbd[i].cbd_datlen = 0;
411 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
412 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600414
415 info->usedTbdIdx = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600417
418 /* Set Rx FIFO alarm and granularity value */
419 fecp->rfcr = 0x0c000000;
420 fecp->rfar = 0x0000030c;
421
422 /* Set Tx FIFO granularity value */
423 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
424 fecp->tfar = 0x00000080;
425
426 fecp->tfwr = 0x2;
427 fecp->ctcwr = 0x03000000;
428
429 /* Enable DMA receive task */
430 MCD_startDma(info->rxTask, /* Dma channel */
431 (s8 *) info->rxbd, /*Source Address */
432 0, /* Source increment */
433 (s8 *) (&fecp->rfdr), /* dest */
434 4, /* dest increment */
435 0, /* DMA size */
436 4, /* xfer size */
437 info->rxInit, /* initiator */
438 info->rxPri, /* priority */
439 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
440 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
441 );
442
443 /* Enable DMA tx task with no ready buffer descriptors */
444 MCD_startDma(info->txTask, /* Dma channel */
445 (s8 *) info->txbd, /*Source Address */
446 0, /* Source increment */
447 (s8 *) (&fecp->tfdr), /* dest */
448 4, /* dest incr */
449 0, /* DMA size */
450 4, /* xfer size */
451 info->txInit, /* initiator */
452 info->txPri, /* priority */
453 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
454 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
455 );
456
457 /* Now enable the transmit and receive processing */
458 fecp->ecr |= FEC_ECR_ETHER_EN;
459
460 return 1;
461}
462
463static void fec_halt(struct eth_device *dev)
464{
465 struct fec_info_dma *info = dev->priv;
466 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
467 int counter = 0xffff;
468
469 /* issue graceful stop command to the FEC transmitter if necessary */
470 fecp->tcr |= FEC_TCR_GTS;
471
472 /* wait for graceful stop to register */
473 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
474
475 /* Disable DMA tasks */
476 MCD_killDma(info->txTask);
Masahiro Yamada51855e82017-06-13 15:17:28 +0900477 MCD_killDma(info->rxTask);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600478
479 /* Disable the Ethernet Controller */
480 fecp->ecr &= ~FEC_ECR_ETHER_EN;
481
482 /* Clear FIFO status registers */
483 fecp->rfsr &= FIFO_ERRSTAT;
484 fecp->tfsr &= FIFO_ERRSTAT;
485
486 fecp->frst = 0x01000000;
487
488 /* Issue a reset command to the FEC chip */
489 fecp->ecr |= FEC_ECR_RESET;
490
491 /* wait at least 20 clock cycles */
492 udelay(10000);
493
494#ifdef ET_DEBUG
495 printf("Ethernet task stopped\n");
496#endif
497}
498
499int mcdmafec_initialize(bd_t * bis)
500{
501 struct eth_device *dev;
502 int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#ifdef CONFIG_SYS_DMA_USE_INTSRAM
504 u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500505#endif
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600506
Axel Lina62cd292013-07-03 11:24:18 +0800507 for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600508
509 dev =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600511 sizeof *dev);
512 if (dev == NULL)
513 hang();
514
515 memset(dev, 0, sizeof(*dev));
516
517 sprintf(dev->name, "FEC%d", fec_info[i].index);
518
519 dev->priv = &fec_info[i];
520 dev->init = fec_init;
521 dev->halt = fec_halt;
522 dev->send = fec_send;
523 dev->recv = fec_recv;
524
525 /* setup Receive and Transmit buffer descriptor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#ifdef CONFIG_SYS_DMA_USE_INTSRAM
TsiChung Liew429be272008-08-21 23:55:11 +0000527 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
528 tmp = (u32)fec_info[i].rxbd;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500529 fec_info[i].txbd =
TsiChung Liew429be272008-08-21 23:55:11 +0000530 (cbd_t *)((u32)fec_info[i].txbd + tmp +
531 (PKTBUFSRX * sizeof(cbd_t)));
532 tmp = (u32)fec_info[i].txbd;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500533 fec_info[i].txbuf =
TsiChung Liew429be272008-08-21 23:55:11 +0000534 (char *)((u32)fec_info[i].txbuf + tmp +
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
TsiChung Liew429be272008-08-21 23:55:11 +0000536 tmp = (u32)fec_info[i].txbuf;
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500537#else
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600538 fec_info[i].rxbd =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600540 (PKTBUFSRX * sizeof(cbd_t)));
541 fec_info[i].txbd =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
543 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600544 fec_info[i].txbuf =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
TsiChung Liewf32f7fe2008-04-30 12:11:19 -0500546#endif
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600547
548#ifdef ET_DEBUG
549 printf("rxbd %x txbd %x\n",
550 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
551#endif
552
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600554
555 eth_register(dev);
556
557#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Joe Hershberger5a49f172016-08-08 11:28:38 -0500558 int retval;
559 struct mii_dev *mdiodev = mdio_alloc();
560 if (!mdiodev)
561 return -ENOMEM;
562 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
563 mdiodev->read = mcffec_miiphy_read;
564 mdiodev->write = mcffec_miiphy_write;
565
566 retval = mdio_register(mdiodev);
567 if (retval < 0)
568 return retval;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600569#endif
570
571 if (i > 0)
572 fec_info[i - 1].next = &fec_info[i];
573 }
574 fec_info[i - 1].next = &fec_info[0];
575
576 /* default speed */
577 bis->bi_ethspeed = 10;
578
Ben Warrenb31da882008-08-26 22:12:36 -0700579 return 0;
TsiChungLiew777d1ab2008-01-15 14:00:25 -0600580}