blob: ee75d1b7eda5d6492aeebfd76ebdc15e62a2242c [file] [log] [blame]
York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
13#include <fdt_support.h>
14#include <libfdt.h>
15#include <fsl_mc.h>
Prabhakar Kushwaha1b357212014-07-14 17:15:44 +053016#include <environment.h>
York Sunf749db32014-06-23 15:15:56 -070017
18DECLARE_GLOBAL_DATA_PTR;
19
20int board_init(void)
21{
22 init_final_memctl_regs();
Prabhakar Kushwaha1b357212014-07-14 17:15:44 +053023
24#ifdef CONFIG_ENV_IS_NOWHERE
25 gd->env_addr = (ulong)&default_environment[0];
26#endif
27
York Sunf749db32014-06-23 15:15:56 -070028 return 0;
29}
30
31int board_early_init_f(void)
32{
33 init_early_memctl_regs(); /* tighten IFC timing */
34
35 return 0;
36}
37
York Sund9c68b12014-08-13 10:21:05 -070038void detail_board_ddr_info(void)
39{
40 puts("\nDDR ");
41 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
42 print_ddr_info(0);
43 if (gd->bd->bi_dram[2].size) {
44 puts("\nDP-DDR ");
45 print_size(gd->bd->bi_dram[2].size, "");
46 print_ddr_info(CONFIG_DP_DDR_CTRL);
47 }
48}
49
York Sunf749db32014-06-23 15:15:56 -070050int dram_init(void)
51{
York Sunf749db32014-06-23 15:15:56 -070052 gd->ram_size = initdram(0);
53
54 return 0;
55}
56
57int timer_init(void)
58{
59 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
60 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
61
York Sun32da3392015-01-06 13:18:43 -080062 /* Enable timebase for all clusters.
63 * It is safe to do so even some clusters are not enabled.
64 */
65 out_le32(cltbenr, 0xf);
66
67 /* Enable clock for timer
68 * This is a global setting.
69 */
70 out_le32(cntcr, 0x1);
York Sunf749db32014-06-23 15:15:56 -070071
72 return 0;
73}
74
75/*
76 * Board specific reset that is system reset.
77 */
78void reset_cpu(ulong addr)
79{
80}
81
82int board_eth_init(bd_t *bis)
83{
84 int error = 0;
85
86#ifdef CONFIG_SMC91111
87 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
88#endif
89
90#ifdef CONFIG_FSL_MC_ENET
91 error = cpu_eth_init(bis);
92#endif
93 return error;
94}
95
96#ifdef CONFIG_FSL_MC_ENET
97void fdt_fixup_board_enet(void *fdt)
98{
99 int offset;
100
101 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
102 if (get_mc_boot_status() == 0)
103 fdt_status_okay(fdt, offset);
104 else
105 fdt_status_fail(fdt, offset);
106}
107#endif
108
109#ifdef CONFIG_OF_BOARD_SETUP
Simon Glasse895a4b2014-10-23 18:58:47 -0600110int ft_board_setup(void *blob, bd_t *bd)
York Sunf749db32014-06-23 15:15:56 -0700111{
112 phys_addr_t base;
113 phys_size_t size;
114
York Sun8bfa3012014-09-08 12:20:01 -0700115 ft_cpu_setup(blob, bd);
116
York Sunf749db32014-06-23 15:15:56 -0700117 /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
118 base = getenv_bootm_low();
119 size = getenv_bootm_size();
120 fdt_fixup_memory(blob, (u64)base, (u64)size);
121
122#ifdef CONFIG_FSL_MC_ENET
123 fdt_fixup_board_enet(blob);
124#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600125
126 return 0;
York Sunf749db32014-06-23 15:15:56 -0700127}
128#endif