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Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +09001/*
2 * Configuation settings for the Renesas Solutions AP-325RXA board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +09008 */
9
10#ifndef __AP325RXA_H
11#define __AP325RXA_H
12
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090013#define CONFIG_CPU_SH7723 1
14#define CONFIG_AP325RXA 1
15
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020016#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090017#undef CONFIG_SHOW_BOOT_PROGRESS
18
19/* SMC9118 */
Ben Warren736fead2009-07-20 22:01:11 -070020#define CONFIG_SMC911X 1
21#define CONFIG_SMC911X_32_BIT 1
22#define CONFIG_SMC911X_BASE 0xB6080000
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090023
24/* MEMORY */
25#define AP325RXA_SDRAM_BASE (0x88000000)
26#define AP325RXA_FLASH_BASE_1 (0xA0000000)
27#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
28
Nobuhiro Iwamatsudb68b702011-01-17 20:46:35 +090029#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
30
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090031/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090033/* Monitor Command Prompt */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090034/* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090036/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090038
39/* SCIF */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090040#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
41#define CONFIG_CONS_SCIF5 1
42
43/* Suppress display of console information at boot */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090044
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
46#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090047
48/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#undef CONFIG_SYS_ALT_MEMTEST
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090050/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#undef CONFIG_SYS_MEMTEST_SCRATCH
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090052
53/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090057/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090059/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090061
62/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090064/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090066/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090069
70/* FLASH */
71#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_FLASH_CFI
73#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090074/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_FLASH_EMPTY_INFO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090076/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090078/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090080
81/*
82 * IDE support
83 */
84#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_PIO_MODE 1
86#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
87#define CONFIG_SYS_IDE_MAXDEVICE 1
88#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
89#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
90#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
91#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
92#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +053093#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090094
95/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_MAX_FLASH_BANKS 1
97#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090098
99/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900101/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900103/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900105/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900107
108/*
109 * Use hardware flash sectors protection instead
110 * of U-Boot software protection
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#undef CONFIG_SYS_FLASH_PROTECTION
113#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900114
115/* ENV setting */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900116#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200117#define CONFIG_ENV_SECT_SIZE (128 * 1024)
118#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
120/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
121#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200122#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900123
124/* Board Clock */
125#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900126#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
127#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200128#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900129
130#endif /* __AP325RXA_H */