Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 7abf0c5886c395a3cc7e11f191d67be9a964a1bf / . / board / stxgp3 / stxgp3.c
blob: df48e772a701dd1058e3959b16f91d3b7741f1cc [file] [log] [blame]
wdenk7abf0c52004-04-18 21:45:42 +0000[diff] [blame^]1/*
2 * (C) Copyright 2003, Embedded Edge, LLC
3 * Dan Malek, <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560
6 *
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31
32extern long int spd_sdram (void);
33
34#include <common.h>
35#include <asm/processor.h>
36#include <asm/immap_85xx.h>
37#include <ioports.h>
38#include <asm/io.h>
39#include <spd.h>
40#include <miiphy.h>
41
42long int fixed_sdram (void);
43
44/*
45 * I/O Port configuration table
46 *
47 * if conf is 1, then that port pin will be configured at boot time
48 * according to the five values podr/pdir/ppar/psor/pdat for that entry
49 */
50
51const iop_conf_t iop_conf_tab[4][32] = {
52
53 /* Port A configuration */
54 { /* conf ppar psor pdir podr pdat */
55 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
56 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
57 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
58 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
59 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
60 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
61 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
62 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
63 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
64 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
65 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
66 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
67 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
68 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
69 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
70 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
71 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
72 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
73 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
74 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
75 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
76 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
77 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
78 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
79 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
80 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
81 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
82 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
83 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
84 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
85 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
86 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
87 },
88
89 /* Port B configuration */
90 { /* conf ppar psor pdir podr pdat */
91 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
92 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
93 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
94 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
95 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
96 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
97 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
98 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
99 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
100 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
101 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
102 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
103 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
104 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
105 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
106 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
107 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
108 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
109 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
110 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
111 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
123 },
124
125 /* Port C */
126 { /* conf ppar psor pdir podr pdat */
127 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
128 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
129 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
130 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
131 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
132 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
133 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
134 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
135 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
136 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
137 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
138 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
139 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
140 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
141 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
142 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
143 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
144 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
145 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
146 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
147 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
148 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
149 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
150 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
151 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
152 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
153 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
154 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
155 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
156 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
157 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
158 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
159 },
160
161 /* Port D */
162 { /* conf ppar psor pdir podr pdat */
163 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
164 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
165 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
166 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
167 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
168 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
169 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
170 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
171 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
172 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
173 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
174 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
175 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
176 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
177 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
178 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
179 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
180 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
181 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
182 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
183 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
184 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
185 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
186 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
187 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
188 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
189 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
190 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
191 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
195 }
196};
197
198static uint64_t blinky_increment;
199static uint64_t next_led_update;
200static uint led_bit;
201
202int board_pre_init (void)
203{
204#if defined(CONFIG_PCI)
205 volatile immap_t *immr = (immap_t *)CFG_IMMR;
206 volatile ccsr_pcix_t *pci = &immr->im_pcix;
207
208 pci->peer &= 0xfffffffdf; /* disable master abort */
209#endif
210 return 0;
211}
212
213void reset_phy (void)
214{
215 volatile uint *blatch;
216
217 blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
218
219 /* reset Giga bit Ethernet port if needed here */
220
221 *blatch &= ~0x000000c0;
222 udelay(100);
223 *blatch = 0x000000c1; /* Light one led, too */
224 udelay(1000);
225
226#if 0 /* This is the port we really want to use for debugging. */
227 /* reset the CPM FEC port */
228#if (CONFIG_ETHER_INDEX == 2)
229 bcsr->bcsr2 &= ~FETH2_RST;
230 udelay(2);
231 bcsr->bcsr2 |= FETH2_RST;
232 udelay(1000);
233#elif (CONFIG_ETHER_INDEX == 3)
234 bcsr->bcsr3 &= ~FETH3_RST;
235 udelay(2);
236 bcsr->bcsr3 |= FETH3_RST;
237 udelay(1000);
238#endif
239#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
240 miiphy_reset(0x0); /* reset PHY */
241 miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
242 miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
243#endif /* CONFIG_MII */
244#endif
245}
246
247int checkboard (void)
248{
249 sys_info_t sysinfo;
250
251 get_sys_info (&sysinfo);
252
253 printf ("Board: Silicon Tx GPPP 8560 Board\n");
254 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
255 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
256 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
257 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
258 || (CFG_LBC_LCRR & 0x0f) == 8) {
259 printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
260 } else {
261 printf("\tLBC: unknown\n");
262 }
263 printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
264 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
265
266 return (0);
267}
268
269/* Blinkin' LEDS for Robert.
270*/
271void
272show_activity(int flag)
273{
274 volatile uint *blatch;
275
276 if (next_led_update > get_ticks())
277 return;
278
279 blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
280
281 led_bit >>= 1;
282 if (led_bit == 0)
283 led_bit = 0x08;
284 *blatch = (0xc0 | led_bit);
285 eieio();
286 next_led_update += (get_tbclk() / 4);
287}
288
289long int initdram (int board_type)
290{
291 long dram_size = 0;
292 extern long spd_sdram (void);
293 volatile immap_t *immap = (immap_t *)CFG_IMMR;
294
295#if defined(CONFIG_DDR_DLL)
296 volatile ccsr_gur_t *gur= &immap->im_gur;
297 uint temp_ddrdll = 0;
298
299 /* Work around to stabilize DDR DLL */
300 temp_ddrdll = gur->ddrdllcr;
301 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
302 asm("sync;isync;msync");
303#endif
304
305 dram_size = spd_sdram ();
306
307#if defined(CONFIG_DDR_ECC)
308 {
309 /* Initialize all of memory for ECC, then
310 * enable errors */
311 uint *p = 0;
312 uint i = 0;
313 volatile immap_t *immap = (immap_t *)CFG_IMMR;
314 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
315 dma_init();
316 for (*p = 0; p < (uint *)(8 * 1024); p++) {
317 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
318 *p = (unsigned int)0xdeadbeef;
319 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
320 }
321
322 /* 8K */
323 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
324 /* 16K */
325 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
326 /* 32K */
327 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
328 /* 64K */
329 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
330 /* 128k */
331 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
332 /* 256k */
333 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
334 /* 512k */
335 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
336 /* 1M */
337 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
338 /* 2M */
339 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
340 /* 4M */
341 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
342
343 for (i = 1; i < dram_size / 0x800000; i++) {
344 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
345 }
346
347 /* Enable errors for ECC */
348 ddr->err_disable = 0x00000000;
349 asm("sync;isync;msync");
350 }
351#endif
352
353 return dram_size;
354}
355
356
357#if defined(CFG_DRAM_TEST)
358int testdram (void)
359{
360 uint *pstart = (uint *) CFG_MEMTEST_START;
361 uint *pend = (uint *) CFG_MEMTEST_END;
362 uint *p;
363
364 printf("SDRAM test phase 1:\n");
365 for (p = pstart; p < pend; p++)
366 *p = 0xaaaaaaaa;
367
368 for (p = pstart; p < pend; p++) {
369 if (*p != 0xaaaaaaaa) {
370 printf ("SDRAM test fails at: %08x\n", (uint) p);
371 return 1;
372 }
373 }
374
375 printf("SDRAM test phase 2:\n");
376 for (p = pstart; p < pend; p++)
377 *p = 0x55555555;
378
379 for (p = pstart; p < pend; p++) {
380 if (*p != 0x55555555) {
381 printf ("SDRAM test fails at: %08x\n", (uint) p);
382 return 1;
383 }
384 }
385
386 printf("SDRAM test passed.\n");
387 return 0;
388}
389#endif
390
391#if !defined(CONFIG_SPD_EEPROM)
392/*************************************************************************
393 * fixed sdram init -- doesn't use serial presence detect.
394 ************************************************************************/
395long int fixed_sdram (void)
396{
397 #ifndef CFG_RAMBOOT
398 volatile immap_t *immap = (immap_t *)CFG_IMMR;
399 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
400
401 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
402 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
403 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
404 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
405 ddr->sdram_mode = CFG_DDR_MODE;
406 ddr->sdram_interval = CFG_DDR_INTERVAL;
407 #if defined (CONFIG_DDR_ECC)
408 ddr->err_disable = 0x0000000D;
409 ddr->err_sbe = 0x00ff0000;
410 #endif
411 asm("sync;isync;msync");
412 udelay(500);
413 #if defined (CONFIG_DDR_ECC)
414 /* Enable ECC checking */
415 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
416 #else
417 ddr->sdram_cfg = CFG_DDR_CONTROL;
418 #endif
419 asm("sync; isync; msync");
420 udelay(500);
421 #endif
422 return ( CFG_SDRAM_SIZE * 1024 * 1024);
423}
424#endif /* !defined(CONFIG_SPD_EEPROM) */