blob: a24d6f3a0fb2e38223d9f58ce86e2c81fd232f0c [file] [log] [blame]
Stefan Roese273ed032010-05-19 11:11:15 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020024#include <asm-offsets.h>
Stefan Roese273ed032010-05-19 11:11:15 +020025#include <ppc_asm.tmpl>
26#include <config.h>
27#include <asm/mmu.h>
28
29/*
30 * TLB TABLE
31 *
32 * This table is used by the cpu boot code to setup the initial tlb
33 * entries. Rather than make broad assumptions in the cpu source tree,
34 * this table lets each board set things up however they like.
35 *
36 * Pointer to the table is returned in r1
37 *
38 */
39 .section .bootpg,"ax"
40 .globl tlbtab
41
42tlbtab:
43 tlbtab_start
44
45 /*
46 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
47 * use the speed up boot process. It is patched after relocation to
48 * enable SA_I
49 */
50 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
51 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
52
53 /*
54 * TLB entries for SDRAM are not needed on this platform.
55 * They are dynamically generated in the DDR(2) detection
56 * routine.
57 */
58
59#ifdef CONFIG_SYS_INIT_RAM_DCACHE
60 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
61 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
62 AC_RWX | SA_G)
63#endif
64
65 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
66 AC_RW | SA_IG)
67 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
68 AC_RW | SA_IG)
69 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
70 AC_RW | SA_IG)
71
72 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
73 AC_RW | SA_IG)
74 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
75 AC_RW | SA_IG)
76 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
77 AC_RW | SA_IG)
78 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
79 AC_RW | SA_IG)
80
81 /* PCIe UTL register */
82 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
83
84 /* TLB-entry for FPGA(s) */
Stefan Roese5bf39a92010-07-19 14:24:22 +020085 tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
Stefan Roese273ed032010-05-19 11:11:15 +020086 AC_RW | SA_IG)
Stefan Roese5bf39a92010-07-19 14:24:22 +020087 tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
88 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
89 tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
Stefan Roese273ed032010-05-19 11:11:15 +020090 AC_RW | SA_IG)
Stefan Roese5bf39a92010-07-19 14:24:22 +020091 tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
Stefan Roese273ed032010-05-19 11:11:15 +020092 AC_RW | SA_IG)
93
94 /* TLB-entry for OCM */
95 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
96 AC_RWX | SA_I)
97
98 /* TLB-entry for Local Configuration registers => peripherals */
99 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
100 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
101
102 tlbtab_end