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gerrit.cesnet.cz / github / trini / u-boot / 7aa1f198c897e48a011f9f0dca6b3088bc474236 / . / arch / mips / cpu / mips32 / start.S
blob: 5d7467d02ad69b6285bba9d598eaf24879e1fe1a [file] [log] [blame]
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]1/*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]25#include <asm-offsets.h>
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]26#include <config.h>
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29
Shinya Kuribayashidecaba62008-03-25 21:30:07 +0900[diff] [blame]30 /*
31 * For the moment disable interrupts, mark the kernel mode and
32 * set ST0_KX so that the CPU does not spit fire when using
33 * 64-bit addresses.
34 */
35 .macro setup_c0_status set clr
36 .set push
37 mfc0 t0, CP0_STATUS
38 or t0, ST0_CU0 | \set | 0x1f | \clr
39 xor t0, 0x1f | \clr
40 mtc0 t0, CP0_STATUS
41 .set noreorder
42 sll zero, 3 # ehb
43 .set pop
44 .endm
45
46 .macro setup_c0_status_reset
47#ifdef CONFIG_64BIT
48 setup_c0_status ST0_KX 0
49#else
50 setup_c0_status 0 0
51#endif
52 .endm
53
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]54#define RVECENT(f,n) \
55 b f; nop
56#define XVECENT(f,bev) \
57 b f ; \
58 li k0,bev
59
60 .set noreorder
61
62 .globl _start
63 .text
64_start:
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]65 RVECENT(reset,0) # U-boot entry point
66 RVECENT(reset,1) # software reboot
67#ifdef CONFIG_INCA_IP
68 .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
69 .word 0x00000000 # booting phase of the flash
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]70#else
71 RVECENT(romReserved,2)
72#endif
73 RVECENT(romReserved,3)
74 RVECENT(romReserved,4)
75 RVECENT(romReserved,5)
76 RVECENT(romReserved,6)
77 RVECENT(romReserved,7)
78 RVECENT(romReserved,8)
79 RVECENT(romReserved,9)
80 RVECENT(romReserved,10)
81 RVECENT(romReserved,11)
82 RVECENT(romReserved,12)
83 RVECENT(romReserved,13)
84 RVECENT(romReserved,14)
85 RVECENT(romReserved,15)
86 RVECENT(romReserved,16)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]87 RVECENT(romReserved,17)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]88 RVECENT(romReserved,18)
89 RVECENT(romReserved,19)
90 RVECENT(romReserved,20)
91 RVECENT(romReserved,21)
92 RVECENT(romReserved,22)
93 RVECENT(romReserved,23)
94 RVECENT(romReserved,24)
95 RVECENT(romReserved,25)
96 RVECENT(romReserved,26)
97 RVECENT(romReserved,27)
98 RVECENT(romReserved,28)
99 RVECENT(romReserved,29)
100 RVECENT(romReserved,30)
101 RVECENT(romReserved,31)
102 RVECENT(romReserved,32)
103 RVECENT(romReserved,33)
104 RVECENT(romReserved,34)
105 RVECENT(romReserved,35)
106 RVECENT(romReserved,36)
107 RVECENT(romReserved,37)
108 RVECENT(romReserved,38)
109 RVECENT(romReserved,39)
110 RVECENT(romReserved,40)
111 RVECENT(romReserved,41)
112 RVECENT(romReserved,42)
113 RVECENT(romReserved,43)
114 RVECENT(romReserved,44)
115 RVECENT(romReserved,45)
116 RVECENT(romReserved,46)
117 RVECENT(romReserved,47)
118 RVECENT(romReserved,48)
119 RVECENT(romReserved,49)
120 RVECENT(romReserved,50)
121 RVECENT(romReserved,51)
122 RVECENT(romReserved,52)
123 RVECENT(romReserved,53)
124 RVECENT(romReserved,54)
125 RVECENT(romReserved,55)
126 RVECENT(romReserved,56)
127 RVECENT(romReserved,57)
128 RVECENT(romReserved,58)
129 RVECENT(romReserved,59)
130 RVECENT(romReserved,60)
131 RVECENT(romReserved,61)
132 RVECENT(romReserved,62)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]133 RVECENT(romReserved,63)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]134 XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]135 RVECENT(romReserved,65)
136 RVECENT(romReserved,66)
137 RVECENT(romReserved,67)
138 RVECENT(romReserved,68)
139 RVECENT(romReserved,69)
140 RVECENT(romReserved,70)
141 RVECENT(romReserved,71)
142 RVECENT(romReserved,72)
143 RVECENT(romReserved,73)
144 RVECENT(romReserved,74)
145 RVECENT(romReserved,75)
146 RVECENT(romReserved,76)
147 RVECENT(romReserved,77)
148 RVECENT(romReserved,78)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]149 RVECENT(romReserved,79)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]150 XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]151 RVECENT(romReserved,81)
152 RVECENT(romReserved,82)
153 RVECENT(romReserved,83)
154 RVECENT(romReserved,84)
155 RVECENT(romReserved,85)
156 RVECENT(romReserved,86)
157 RVECENT(romReserved,87)
158 RVECENT(romReserved,88)
159 RVECENT(romReserved,89)
160 RVECENT(romReserved,90)
161 RVECENT(romReserved,91)
162 RVECENT(romReserved,92)
163 RVECENT(romReserved,93)
164 RVECENT(romReserved,94)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]165 RVECENT(romReserved,95)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]166 XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]167 RVECENT(romReserved,97)
168 RVECENT(romReserved,98)
169 RVECENT(romReserved,99)
170 RVECENT(romReserved,100)
171 RVECENT(romReserved,101)
172 RVECENT(romReserved,102)
173 RVECENT(romReserved,103)
174 RVECENT(romReserved,104)
175 RVECENT(romReserved,105)
176 RVECENT(romReserved,106)
177 RVECENT(romReserved,107)
178 RVECENT(romReserved,108)
179 RVECENT(romReserved,109)
180 RVECENT(romReserved,110)
181 RVECENT(romReserved,111)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]182 XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]183 RVECENT(romReserved,113)
184 RVECENT(romReserved,114)
185 RVECENT(romReserved,115)
186 RVECENT(romReserved,116)
187 RVECENT(romReserved,116)
188 RVECENT(romReserved,118)
189 RVECENT(romReserved,119)
190 RVECENT(romReserved,120)
191 RVECENT(romReserved,121)
192 RVECENT(romReserved,122)
193 RVECENT(romReserved,123)
194 RVECENT(romReserved,124)
195 RVECENT(romReserved,125)
196 RVECENT(romReserved,126)
197 RVECENT(romReserved,127)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]198
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]199 /*
200 * We hope there are no more reserved vectors!
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]201 * 128 * 8 == 1024 == 0x400
202 * so this is address R_VEC+0x400 == 0xbfc00400
203 */
204 .align 4
205reset:
206
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]207 /* Clear watch registers */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]208 mtc0 zero, CP0_WATCHLO
209 mtc0 zero, CP0_WATCHHI
210
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]211 /* WP(Watch Pending), SW0/1 should be cleared */
Shinya Kuribayashid43d43e2008-03-25 21:30:07 +0900[diff] [blame]212 mtc0 zero, CP0_CAUSE
213
Shinya Kuribayashidecaba62008-03-25 21:30:07 +0900[diff] [blame]214 setup_c0_status_reset
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]215
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]216 /* Init Timer */
217 mtc0 zero, CP0_COUNT
218 mtc0 zero, CP0_COMPARE
219
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]220#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]221 /* CONFIG0 register */
222 li t0, CONF_CM_UNCACHED
223 mtc0 t0, CP0_CONFIG
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]224#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]225
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]226 /* Initialize $gp */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]227 bal 1f
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]228 nop
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]229 .word _gp
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]2301:
Shinya Kuribayashi16664f72007-11-17 20:05:26 +0900[diff] [blame]231 lw gp, 0(ra)
Wolfgang Denkc75eba32005-12-01 02:15:07 +0100[diff] [blame]232
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]233#ifndef CONFIG_SKIP_LOWLEVEL_INIT
234 /* Initialize any external memory */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]235 la t9, lowlevel_init
236 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]237 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]238
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]239 /* Initialize caches... */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]240 la t9, mips_cache_reset
241 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]242 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]243
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]244 /* ... and enable them */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]245 li t0, CONF_CM_CACHABLE_NONCOHERENT
246 mtc0 t0, CP0_CONFIG
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]247#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]248
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]249 /* Set up temporary stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]250 li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]251 la sp, 0(t0)
252
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]253 la t9, board_init_f
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]254 jr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]255 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]256
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]257/*
258 * void relocate_code (addr_sp, gd, addr_moni)
259 *
260 * This "function" does not return, instead it continues in RAM
261 * after relocating the monitor code.
262 *
263 * a0 = addr_sp
264 * a1 = gd
265 * a2 = destination address
266 */
267 .globl relocate_code
268 .ent relocate_code
269relocate_code:
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]270 move sp, a0 # set new stack pointer
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]272 li t0, CONFIG_SYS_MONITOR_BASE
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]273 la t3, in_ram
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]274 lw t2, -12(t3) # t2 <-- uboot_end_data
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]275 move t1, a2
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]276 move s2, a2 # s2 <-- destination address
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]277
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]278 /*
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]279 * Fix $gp:
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]280 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]281 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]282 */
283 move t6, gp
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]284 sub gp, CONFIG_SYS_MONITOR_BASE
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]285 add gp, a2 # gp now adjusted
286 sub s1, gp, t6 # s1 <-- relocation offset
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]287
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]288 /*
289 * t0 = source address
290 * t1 = target address
291 * t2 = source end address
292 */
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]293
294 /*
295 * Save destination address and size for later usage in flush_cache()
296 */
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]297 move s0, a1 # save gd in s0
298 move a0, t1 # a0 <-- destination addr
299 sub a1, t2, t0 # a1 <-- size
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]300
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]3011:
302 lw t3, 0(t0)
303 sw t3, 0(t1)
304 addu t0, 4
305 ble t0, t2, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]306 addu t1, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]307
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]308 /* If caches were enabled, we would have to flush them here. */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]309
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]310 /* a0 & a1 are already set up for flush_cache(start, size) */
311 la t9, flush_cache
312 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]313 nop
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]314
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]315 /* Jump to where we've relocated ourselves */
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]316 addi t0, s2, in_ram - _start
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]317 jr t0
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]318 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]319
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]320 .word _gp
Vlad Lungu0f8c62a2008-05-05 14:04:00 +0300[diff] [blame]321 .word _GLOBAL_OFFSET_TABLE_
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]322 .word uboot_end_data
323 .word uboot_end
324 .word num_got_entries
325
326in_ram:
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]327 /*
328 * Now we want to update GOT.
329 *
330 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
331 * generated by GNU ld. Skip these reserved entries from relocation.
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]332 */
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]333 lw t3, -4(t0) # t3 <-- num_got_entries
334 lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
335 lw t5, -20(t0) # t5 <-- _gp
336 sub t4, t5 # compute offset
337 add t4, t4, gp # t4 now holds relocated _G_O_T_
338 addi t4, t4, 8 # skipping first two entries
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]339 li t2, 2
3401:
341 lw t1, 0(t4)
342 beqz t1, 2f
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]343 add t1, s1
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]344 sw t1, 0(t4)
3452:
346 addi t2, 1
347 blt t2, t3, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]348 addi t4, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]349
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]350 /* Clear BSS */
351 lw t1, -12(t0) # t1 <-- uboot_end_data
352 lw t2, -8(t0) # t2 <-- uboot_end
353 add t1, s1 # adjust pointers
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]354 add t2, s1
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]355
356 sub t1, 4
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]3571:
358 addi t1, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]359 bltl t1, t2, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]360 sw zero, 0(t1)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]361
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]362 move a0, s0 # a0 <-- gd
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]363 la t9, board_init_r
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]364 jr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]365 move a1, s2
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]366
367 .end relocate_code
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]368
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame^]369 /* Exception handlers */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]370romReserved:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]371 b romReserved
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]372
373romExcHandle:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]374 b romExcHandle