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Ed Swarthout63cec582007-08-02 14:09:49 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16 * MA 02111-1307 USA
17 */
Ed Swarthout2e4d94f2007-07-27 01:50:45 -050018
Ed Swarthout63cec582007-08-02 14:09:49 -050019#include <common.h>
20
Kumar Galab9a1fa92008-10-22 14:06:24 -050021DECLARE_GLOBAL_DATA_PTR;
22
Ed Swarthout63cec582007-08-02 14:09:49 -050023/*
24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
25 *
26 * Initialize controller and call the common driver/pci pci_hose_scan to
27 * scan for bridges and devices.
28 *
29 * Hose fields which need to be pre-initialized by board specific code:
30 * regions[]
31 * first_busno
32 *
33 * Fields updated:
34 * last_busno
35 */
36
37#include <pci.h>
38#include <asm/immap_fsl_pci.h>
39
Peter Tyser7a897952008-10-29 12:39:26 -050040/* Freescale-specific PCI config registers */
41#define FSL_PCI_PBFR 0x44
42#define FSL_PCIE_CAP_ID 0x4c
43#define FSL_PCIE_CFG_RDY 0x4b0
44
Ed Swarthout63cec582007-08-02 14:09:49 -050045void pciauto_prescan_setup_bridge(struct pci_controller *hose,
46 pci_dev_t dev, int sub_bus);
47void pciauto_postscan_setup_bridge(struct pci_controller *hose,
48 pci_dev_t dev, int sub_bus);
Ed Swarthout63cec582007-08-02 14:09:49 -050049void pciauto_config_init(struct pci_controller *hose);
Kumar Gala612ea012008-10-21 10:13:14 -050050
Kumar Galab9a1fa92008-10-22 14:06:24 -050051#ifndef CONFIG_SYS_PCI_MEMORY_BUS
52#define CONFIG_SYS_PCI_MEMORY_BUS 0
53#endif
54
55#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
56#define CONFIG_SYS_PCI_MEMORY_PHYS 0
57#endif
58
59#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
60#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
61#endif
62
63int fsl_pci_setup_inbound_windows(struct pci_region *r)
64{
65 struct pci_region *rgn_base = r;
Becky Bruce35db1c62008-11-21 19:24:22 -060066 u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
Kumar Galab9a1fa92008-10-22 14:06:24 -050067
68 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
69 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
70 pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
71
72 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
73 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
74 pci_set_region(r++, bus_start, phys_start, pci_sz,
Kumar Gala219542a2008-10-27 13:16:20 -050075 PCI_REGION_MEM | PCI_REGION_MEMORY |
Kumar Galab9a1fa92008-10-22 14:06:24 -050076 PCI_REGION_PREFETCH);
77
78 sz -= pci_sz;
79 bus_start += pci_sz;
80 phys_start += pci_sz;
81
82 pci_sz = 1ull << __ilog2_u64(sz);
83 if (sz) {
84 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
85 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
86 pci_set_region(r++, bus_start, phys_start, pci_sz,
Kumar Gala219542a2008-10-27 13:16:20 -050087 PCI_REGION_MEM | PCI_REGION_MEMORY |
Kumar Galab9a1fa92008-10-22 14:06:24 -050088 PCI_REGION_PREFETCH);
89 sz -= pci_sz;
90 bus_start += pci_sz;
91 phys_start += pci_sz;
92 }
93
94#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
Becky Brucecd425162008-10-27 16:09:42 -050095 /*
96 * On 64-bit capable systems, set up a mapping for all of DRAM
97 * in high pci address space.
98 */
Kumar Galab9a1fa92008-10-22 14:06:24 -050099 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
100 /* round up to the next largest power of two */
101 if (gd->ram_size > pci_sz)
Becky Brucecd425162008-10-27 16:09:42 -0500102 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
Kumar Galab9a1fa92008-10-22 14:06:24 -0500103 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
Becky Brucecd425162008-10-27 16:09:42 -0500104 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
Kumar Galab9a1fa92008-10-22 14:06:24 -0500105 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
106 (u64)pci_sz);
107 pci_set_region(r++,
Becky Brucecd425162008-10-27 16:09:42 -0500108 CONFIG_SYS_PCI64_MEMORY_BUS,
Kumar Galab9a1fa92008-10-22 14:06:24 -0500109 CONFIG_SYS_PCI_MEMORY_PHYS,
110 pci_sz,
Kumar Gala219542a2008-10-27 13:16:20 -0500111 PCI_REGION_MEM | PCI_REGION_MEMORY |
Kumar Galab9a1fa92008-10-22 14:06:24 -0500112 PCI_REGION_PREFETCH);
113#else
114 pci_sz = 1ull << __ilog2_u64(sz);
115 if (sz) {
116 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
117 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
118 pci_set_region(r++, bus_start, phys_start, pci_sz,
Kumar Gala219542a2008-10-27 13:16:20 -0500119 PCI_REGION_MEM | PCI_REGION_MEMORY |
Kumar Galab9a1fa92008-10-22 14:06:24 -0500120 PCI_REGION_PREFETCH);
121 sz -= pci_sz;
122 bus_start += pci_sz;
123 phys_start += pci_sz;
124 }
125#endif
126
Kumar Gala4c253fd2008-12-09 10:27:33 -0600127#ifdef CONFIG_PHYS_64BIT
Kumar Galab9a1fa92008-10-22 14:06:24 -0500128 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
129 printf("Was not able to map all of memory via "
130 "inbound windows -- %lld remaining\n", sz);
Kumar Gala4c253fd2008-12-09 10:27:33 -0600131#endif
Kumar Galab9a1fa92008-10-22 14:06:24 -0500132
133 return r - rgn_base;
134}
135
Kumar Gala612ea012008-10-21 10:13:14 -0500136void fsl_pci_init(struct pci_controller *hose)
Ed Swarthout63cec582007-08-02 14:09:49 -0500137{
138 u16 temp16;
139 u32 temp32;
140 int busno = hose->first_busno;
141 int enabled;
142 u16 ltssm;
143 u8 temp8;
144 int r;
145 int bridge;
Ed Swarthoutcb8250f2007-10-19 17:51:40 -0500146 int inbound = 0;
Ed Swarthout63cec582007-08-02 14:09:49 -0500147 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
148 pci_dev_t dev = PCI_BDF(busno,0,0);
149
150 /* Initialize ATMU registers based on hose regions and flags */
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200151 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
152 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
Ed Swarthout63cec582007-08-02 14:09:49 -0500153
154#ifdef DEBUG
155 int neg_link_w;
156#endif
157
158 for (r=0; r<hose->region_count; r++) {
Kumar Gala612ea012008-10-21 10:13:14 -0500159 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
Ed Swarthout63cec582007-08-02 14:09:49 -0500160 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
Kumar Gala219542a2008-10-27 13:16:20 -0500161 u32 flag = PIWAR_EN | PIWAR_LOCAL |
Kumar Gala612ea012008-10-21 10:13:14 -0500162 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
163 pi->pitar = (hose->regions[r].phys_start >> 12);
164 pi->piwbar = (hose->regions[r].bus_start >> 12);
165#ifdef CONFIG_SYS_PCI_64BIT
166 pi->piwbear = (hose->regions[r].bus_start >> 44);
167#else
Ed Swarthout63cec582007-08-02 14:09:49 -0500168 pi->piwbear = 0;
Kumar Gala612ea012008-10-21 10:13:14 -0500169#endif
170 if (hose->regions[r].flags & PCI_REGION_PREFETCH)
171 flag |= PIWAR_PF;
172 pi->piwar = flag | sz;
Ed Swarthout63cec582007-08-02 14:09:49 -0500173 pi++;
Ed Swarthoutcb8250f2007-10-19 17:51:40 -0500174 inbound = hose->regions[r].size > 0;
Ed Swarthout63cec582007-08-02 14:09:49 -0500175 } else { /* Outbound */
Kumar Gala612ea012008-10-21 10:13:14 -0500176 po->powbar = (hose->regions[r].phys_start >> 12);
177 po->potar = (hose->regions[r].bus_start >> 12);
178#ifdef CONFIG_SYS_PCI_64BIT
179 po->potear = (hose->regions[r].bus_start >> 44);
180#else
Ed Swarthout63cec582007-08-02 14:09:49 -0500181 po->potear = 0;
Kumar Gala612ea012008-10-21 10:13:14 -0500182#endif
Ed Swarthout63cec582007-08-02 14:09:49 -0500183 if (hose->regions[r].flags & PCI_REGION_IO)
Kumar Gala219542a2008-10-27 13:16:20 -0500184 po->powar = POWAR_EN | sz |
Kumar Gala612ea012008-10-21 10:13:14 -0500185 POWAR_IO_READ | POWAR_IO_WRITE;
Ed Swarthout63cec582007-08-02 14:09:49 -0500186 else
Kumar Gala219542a2008-10-27 13:16:20 -0500187 po->powar = POWAR_EN | sz |
Kumar Gala612ea012008-10-21 10:13:14 -0500188 POWAR_MEM_READ | POWAR_MEM_WRITE;
Ed Swarthout63cec582007-08-02 14:09:49 -0500189 po++;
190 }
191 }
192
193 pci_register_hose(hose);
194 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
195 hose->current_busno = hose->first_busno;
196
197 pci->pedr = 0xffffffff; /* Clear any errors */
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500198 pci->peer = ~0x20140; /* Enable All Error Interupts except
199 * - Master abort (pci)
200 * - Master PERR (pci)
201 * - ICCA (PCIe)
202 */
Ed Swarthout63cec582007-08-02 14:09:49 -0500203 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
204 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
205 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
206
207 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
208 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
209
210 if ( bridge ) {
211
212 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
213 enabled = ltssm >= PCI_LTSSM_L0;
214
Kumar Gala8ff3de62007-12-07 12:17:34 -0600215#ifdef CONFIG_FSL_PCIE_RESET
216 if (ltssm == 1) {
217 int i;
218 debug("....PCIe link error. "
219 "LTSSM=0x%02x.", ltssm);
220 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
221 temp32 = pci->pdb_stat;
222 udelay(100);
223 debug(" Asserting PCIe reset @%x = %x\n",
224 &pci->pdb_stat, pci->pdb_stat);
225 pci->pdb_stat &= ~0x08000000; /* clear reset */
226 asm("sync;isync");
227 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
228 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
229 &ltssm);
230 udelay(1000);
231 debug("....PCIe link error. "
232 "LTSSM=0x%02x.\n", ltssm);
233 }
234 enabled = ltssm >= PCI_LTSSM_L0;
235 }
236#endif
237
Ed Swarthout63cec582007-08-02 14:09:49 -0500238 if (!enabled) {
239 debug("....PCIE link error. Skipping scan."
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500240 "LTSSM=0x%02x\n", ltssm);
Ed Swarthout63cec582007-08-02 14:09:49 -0500241 hose->last_busno = hose->first_busno;
242 return;
243 }
244
245 pci->pme_msg_det = 0xffffffff;
246 pci->pme_msg_int_en = 0xffffffff;
247#ifdef DEBUG
248 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
249 neg_link_w = (temp16 & 0x3f0 ) >> 4;
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500250 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
Ed Swarthout63cec582007-08-02 14:09:49 -0500251 ltssm, neg_link_w);
252#endif
253 hose->current_busno++; /* Start scan with secondary */
254 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
255
Ed Swarthout63cec582007-08-02 14:09:49 -0500256 }
257
Ed Swarthout16e23c32007-08-20 23:55:33 -0500258 /* Use generic setup_device to initialize standard pci regs,
259 * but do not allocate any windows since any BAR found (such
260 * as PCSRBAR) is not in this cpu's memory space.
261 */
Ed Swarthout1900fbf2007-08-30 02:26:17 -0500262
Ed Swarthout16e23c32007-08-20 23:55:33 -0500263 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
Ed Swarthout63cec582007-08-02 14:09:49 -0500264 hose->pci_prefetch, hose->pci_io);
Ed Swarthout16e23c32007-08-20 23:55:33 -0500265
Ed Swarthoutcb8250f2007-10-19 17:51:40 -0500266 if (inbound) {
267 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
268 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
269 temp16 | PCI_COMMAND_MEMORY);
270 }
271
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500272#ifndef CONFIG_PCI_NOSCAN
Ed Swarthout6df0efd2008-10-08 23:38:00 -0500273 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
274
275 /* Programming Interface (PCI_CLASS_PROG)
276 * 0 == pci host or pcie root-complex,
277 * 1 == pci agent or pcie end-point
278 */
279 if (!temp8) {
280 printf(" Scanning PCI bus %02x\n",
281 hose->current_busno);
282 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
283 } else {
284 debug(" Not scanning PCI bus %02x. PI=%x\n",
285 hose->current_busno, temp8);
286 hose->last_busno = hose->current_busno;
287 }
Ed Swarthout63cec582007-08-02 14:09:49 -0500288
289 if ( bridge ) { /* update limit regs and subordinate busno */
290 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
291 }
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500292#else
293 hose->last_busno = hose->current_busno;
294#endif
Ed Swarthout63cec582007-08-02 14:09:49 -0500295
296 /* Clear all error indications */
297
Kumar Gala876b8f92008-04-23 16:58:04 -0500298 if (bridge)
299 pci->pme_msg_det = 0xffffffff;
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500300 pci->pedr = 0xffffffff;
Ed Swarthout63cec582007-08-02 14:09:49 -0500301
302 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
303 if (temp16) {
Ed Swarthout63cec582007-08-02 14:09:49 -0500304 pci_hose_write_config_word(hose, dev,
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500305 PCI_DSR, 0xffff);
Ed Swarthout63cec582007-08-02 14:09:49 -0500306 }
307
308 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
309 if (temp16) {
Ed Swarthout63cec582007-08-02 14:09:49 -0500310 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
311 }
312}
Kumar Galaa2aab462008-10-23 00:01:06 -0500313
Peter Tyser7a897952008-10-29 12:39:26 -0500314/* Enable inbound PCI config cycles for agent/endpoint interface */
315void fsl_pci_config_unlock(struct pci_controller *hose)
316{
317 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
318 u8 agent;
319 u8 pcie_cap;
320 u16 pbfr;
321
322 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
323 if (!agent)
324 return;
325
326 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
327 if (pcie_cap != 0x0) {
328 /* PCIe - set CFG_READY bit of Configuration Ready Register */
329 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
330 } else {
331 /* PCI - clear ACL bit of PBFR */
332 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
333 pbfr &= ~0x20;
334 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
335 }
336}
337
Kumar Galaa2aab462008-10-23 00:01:06 -0500338#ifdef CONFIG_OF_BOARD_SETUP
339#include <libfdt.h>
340#include <fdt_support.h>
341
342void ft_fsl_pci_setup(void *blob, const char *pci_alias,
343 struct pci_controller *hose)
344{
345 int off = fdt_path_offset(blob, pci_alias);
346
347 if (off >= 0) {
348 u32 bus_range[2];
349
350 bus_range[0] = 0;
351 bus_range[1] = hose->last_busno - hose->first_busno;
352 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
353 fdt_pci_dma_ranges(blob, off, hose);
354 }
355}
356#endif