blob: fddba92389c0f5774fdd20f5044d9613f47397e7 [file] [log] [blame]
Heiko Schocher62ddcf02010-02-18 08:08:25 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * (C) Copyright 2010
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher62ddcf02010-02-18 08:08:25 +010015 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/*
21 * High Level Configuration Options
22 */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010023
Gerlando Falautoc4d22de2012-10-10 22:13:10 +000024/* This needs to be set prior to including km/km83xx-common.h */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010025#define CONFIG_SYS_TEXT_BASE 0xF0000000
Heiko Schocher62ddcf02010-02-18 08:08:25 +010026
Gerlando Falautoc4d22de2012-10-10 22:13:10 +000027#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
28#define CONFIG_HOSTNAME suvd3
29#define CONFIG_KM_BOARD_NAME "suvd3"
Heiko Schocher8ed74342011-03-08 10:47:39 +010030/* include common defines/options for all 8321 Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +000031#include "km/km8321-common.h"
Gerlando Falautoc4d22de2012-10-10 22:13:10 +000032#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
33#define CONFIG_HOSTNAME kmvect1
34#define CONFIG_KM_BOARD_NAME "kmvect1"
35/* include common defines/options for all 8309 Keymile boards */
36#include "km/km8309-common.h"
37#else
38#error Supported boards are: SUVD3, KMVECT1
39#endif
Heiko Schocher62ddcf02010-02-18 08:08:25 +010040
Heiko Schocher62ddcf02010-02-18 08:08:25 +010041#define CONFIG_SYS_APP1_BASE 0xA0000000
Gerlando Falauto91eb52ad2012-10-10 22:13:05 +000042#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010043#define CONFIG_SYS_APP2_BASE 0xB0000000
Gerlando Falauto91eb52ad2012-10-10 22:13:05 +000044#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010045
46/* EEprom support */
47#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
48
49/*
Heiko Schocher62ddcf02010-02-18 08:08:25 +010050 * Init Local Bus Memory Controller:
51 *
52 * Bank Bus Machine PortSz Size Device
53 * ---- --- ------- ------ ----- ------
54 * 2 Local UPMA 16 bit 256MB APP1
55 * 3 Local GPCM 16 bit 256MB APP2
56 *
57 */
58
59/*
60 * APP1 on the local bus CS2
61 */
62#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
63#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
64
65#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
66 BR_PS_16 | \
67 BR_MS_UPMA | \
68 BR_V)
69#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
70
71#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
72 BR_PS_16 | \
73 BR_V)
74
75#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
76 OR_GPCM_CSNT | \
77 OR_GPCM_ACS_DIV4 | \
78 OR_GPCM_SCY_3 | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -050079 OR_GPCM_TRLX_SET)
Heiko Schocher62ddcf02010-02-18 08:08:25 +010080
81#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
82 0x0000c000 | \
83 MxMR_WLFx_2X)
84
85#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
86#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
87
88/*
89 * MMU Setup
90 */
91
92
93/* APP1: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -050094#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +010095 BATL_MEMCOHERENCE)
96#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
97 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -050098#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +010099 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
100#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
101
Joe Hershberger72cd4082011-10-11 23:57:28 -0500102#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100103 BATL_MEMCOHERENCE)
104#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
105 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500106#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100107 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
108#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
109
Karlheinz Jerg5bcd64c2013-01-21 03:55:18 +0000110/*
111 * QE UEC ethernet configuration
112 */
113#if defined(CONFIG_KMVECT1)
114#define CONFIG_MV88E6352_SWITCH
115#define CONFIG_KM_MVEXTSW_ADDR 0x10
116
117/* ethernet port connected to simple switch 88e6122 (UEC0) */
118#define CONFIG_UEC_ETH1
119#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
120#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
121#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
122
123#define CONFIG_FIXED_PHY 0xFFFFFFFF
124#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
125#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
126 {devnum, speed, duplex}
127#define CONFIG_SYS_FIXED_PHY_PORTS \
128 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
129
130#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
131#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
132#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
133#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
134
135/* ethernet port connected to piggy (UEC2) */
136#define CONFIG_HAS_ETH1
137#define CONFIG_UEC_ETH2
138#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
139#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
140#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
141#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
142#define CONFIG_SYS_UEC2_PHY_ADDR 0
143#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
144#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
145#endif /* CONFIG_KMVECT1 */
146
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100147#endif /* __CONFIG_H */