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wdenk608c9142003-01-13 23:54:46 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_V37 1 /* ...on a Marel V37 board */
38
39#define CONFIG_LCD
40#define CONFIG_SHARP_LQ084V1DG21
41#undef CONFIG_LCD_LOGO
42
43/*-----------------------------------------------------------------------------
44 * I2C Configuration
45 *-----------------------------------------------------------------------------
46 */
47#define CONFIG_I2C 1
48#define CFG_I2C_SLAVE 0x2
49
50#define CONFIG_8xx_CONS_SMC1 1
51#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
52#undef CONFIG_8xx_CONS_NONE
53#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */
54#if 0
55#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
56#else
57#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
58#endif
59
60#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
61#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
62
63#undef CONFIG_BOOTARGS
64
65#define CONFIG_BOOTCOMMAND \
66 "tftpboot; " \
67 "setenv bootargs console=tty0 " \
68 "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
69 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
70 "bootm"
71
72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
73#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
74
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
78
79#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
80
81#define CONFIG_MAC_PARTITION
82#define CONFIG_DOS_PARTITION
83
84#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
85
86#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
87 CFG_CMD_JFFS2 | \
88 CFG_CMD_DATE )
89
90
91/* Flash banks JFFS2 should use */
92#define CFG_JFFS2_FIRST_BANK 1
93#define CFG_JFFS2_NUM_BANKS 1
94
95/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
96#include <cmd_confdefs.h>
97
98/*
99 * Miscellaneous configurable options
100 */
101#define CFG_LONGHELP /* undef to save memory */
102#define CFG_PROMPT "=> " /* Monitor Command Prompt */
103#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
104#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
105#else
106#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107#endif
108#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
109#define CFG_MAXARGS 16 /* max number of command args */
110#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
111
112#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
113#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
114
115#define CFG_LOAD_ADDR 0x100000 /* default load address */
116
117#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
118
119#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
120
121/*
122 * Low Level Configuration Settings
123 * (address mappings, register initial values, etc.)
124 * You should know what you are doing if you make changes here.
125 */
126/*-----------------------------------------------------------------------
127 * Internal Memory Mapped Register
128 */
129#define CFG_IMMR 0xF0000000
130
131/*-----------------------------------------------------------------------
132 * Definitions for initial stack pointer and data area (in DPRAM)
133 */
134#define CFG_INIT_RAM_ADDR CFG_IMMR
135#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
136#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
137#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
138#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
139
140/*-----------------------------------------------------------------------
141 * Start addresses for the final memory configuration
142 * (Set up by the startup code)
143 * Please note that CFG_SDRAM_BASE _must_ start at 0
144 */
145#define CFG_SDRAM_BASE 0x00000000
146#define CFG_FLASH_BASE0 0x40000000
147#define CFG_FLASH_BASE1 0x60000000
148#define CFG_FLASH_BASE CFG_FLASH_BASE1
149
150#if defined(DEBUG)
151#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
152#else
153#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
154#endif
155#define CFG_MONITOR_BASE CFG_FLASH_BASE0
156#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
157
158/*
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization.
162 */
163#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
164
165/*-----------------------------------------------------------------------
166 * FLASH organization
167 */
168#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
169#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
170
171#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
172#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
173
174#define CFG_ENV_IS_IN_NVRAM 1
175#define CFG_ENV_ADDR 0x80000000/* Address of Environment */
176#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
177
178#define CFG_ENV_OFFSET 0
179
180/*-----------------------------------------------------------------------
181 * Cache Configuration
182 */
183#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
184#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
185#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
186#endif
187
188/*-----------------------------------------------------------------------
189 * SYPCR - System Protection Control 11-9
190 * SYPCR can only be written once after reset!
191 *-----------------------------------------------------------------------
192 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
193 */
194#if defined(CONFIG_WATCHDOG)
195#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
196 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
197#else
198#define CFG_SYPCR 0xFFFFFF88
199#endif
200
201/*-----------------------------------------------------------------------
202 * SIUMCR - SIU Module Configuration 11-6
203 *-----------------------------------------------------------------------
204 * PCMCIA config., multi-function pin tri-state
205 */
206#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
207
208/*-----------------------------------------------------------------------
209 * TBSCR - Time Base Status and Control 11-26
210 *-----------------------------------------------------------------------
211 * Clear Reference Interrupt Status, Timebase freezing enabled
212 */
213#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
214
215/*-----------------------------------------------------------------------
216 * RTCSC - Real-Time Clock Status and Control Register 11-27
217 *-----------------------------------------------------------------------
218 */
219/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
220#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
221
222/*-----------------------------------------------------------------------
223 * PISCR - Periodic Interrupt Status and Control 11-31
224 *-----------------------------------------------------------------------
225 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
226 */
227#define CFG_PISCR (PISCR_PS | PISCR_PITF)
228/*
229#define CFG_PISCR (PISCR_PS | PISCR_PITF)
230*/
231
232/*-----------------------------------------------------------------------
233 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
234 *-----------------------------------------------------------------------
235 * Reset PLL lock status sticky bit, timer expired status bit and timer
236 * interrupt status bit
237 *
238 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
239 */
240/* up to 50 MHz we use a 1:1 clock */
241#define CFG_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
242
243/*-----------------------------------------------------------------------
244 * SCCR - System Clock and reset Control Register 15-27
245 *-----------------------------------------------------------------------
246 * Set clock output, timebase and RTC source and divider,
247 * power management and some other internal clocks
248 */
249#define SCCR_MASK SCCR_EBDF11
250/* up to 50 MHz we use a 1:1 clock */
251#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
252
253/*-----------------------------------------------------------------------
254 * PCMCIA stuff
255 *-----------------------------------------------------------------------
256 *
257 */
258#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
259#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
260#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
261#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
262#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
263#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
264#define CFG_PCMCIA_IO_ADDR (0xEC000000)
265#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
266
267/*-----------------------------------------------------------------------
268 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
269 *-----------------------------------------------------------------------
270 */
271
272#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */
273
274#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
275#undef CONFIG_IDE_LED /* LED for ide not supported */
276#undef CONFIG_IDE_RESET /* reset for ide not supported */
277
278#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
279#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
280
281#define CFG_ATA_IDE0_OFFSET 0x0000
282
283#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
284
285/* Offset for data I/O */
286#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
287
288/* Offset for normal register accesses */
289#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
290
291/* Offset for alternate registers */
292#define CFG_ATA_ALT_OFFSET 0x0100
293
294/*-----------------------------------------------------------------------
295 *
296 *-----------------------------------------------------------------------
297 *
298 */
wdenk2535d602003-07-17 23:16:40 +0000299#define CFG_DER 0
wdenk608c9142003-01-13 23:54:46 +0000300
301/*
302 * Init Memory Controller:
303 *
304 * BR0 and OR0 (FLASH)
305 */
306
307#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
308#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
309
310#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
311
312#define CFG_OR_TIMING_FLASH 0xF56
313
314#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
315#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
316
317#define CFG_OR5_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
318#define CFG_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
319
320/*
321 * BR1 and OR1 (Battery backed SRAM)
322 */
323#define CFG_BR1_PRELIM 0x80000401
324#define CFG_OR1_PRELIM 0xFFC00736
325
326/*
327 * BR2 and OR2 (SDRAM)
328 */
329#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
330#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */
331
332#define CFG_OR_TIMING_SDRAM 0x00000A00
333
334#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
335#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
336
337/* Marel V37 mem setting */
338
339#define CFG_BR3_CAN 0xC0000401
340#define CFG_OR3_CAN 0xFFFF0724
341
342/*
343#define CFG_BR3_PRELIM 0xFA400001
344#define CFG_OR3_PRELIM 0xFFFF8910
345#define CFG_BR4_PRELIM 0xFA000401
346#define CFG_OR4_PRELIM 0xFFFE0970
347*/
348
349/*
350 * Memory Periodic Timer Prescaler
351 */
352
353/* periodic timer for refresh */
354#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
355
356/*
357 * Refresh clock Prescalar
358 */
359#define CFG_MPTPR MPTPR_PTP_DIV16
360
361/*
362 * MAMR settings for SDRAM
363 */
364
365/* 10 column SDRAM */
366#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
367 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
368 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
369
370/*
371 * Internal Definitions
372 *
373 * Boot Flags
374 */
375#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
376#define BOOTFLAG_WARM 0x02 /* Software reboot */
377
wdenk608c9142003-01-13 23:54:46 +0000378#endif /* __CONFIG_H */