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Wolfgang Denk32cb2c72006-07-21 11:31:42 +02001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02005 * Gary Jennejohn <garyj@denx.de>
Wolfgang Denk32cb2c72006-07-21 11:31:42 +02006 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Modified for the friendly-arm SBC-2410X by
9 * (C) Copyright 2005
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11 *
12 * Configuation settings for the friendly-arm SBC-2410X board.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*
37 * If we are developing, we might want to start armboot from ram
38 * so we MUST NOT initialize critical regs like mem-timing ...
39 */
40#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
41
42/*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
47#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
48#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
49
50/* input clock of PLL */
51#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
52
53
54#define USE_920T_MMU 1
55#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
56
57/*
58 * Size of malloc() pool
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
61#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020062
63/*
64 * Hardware drivers
65 */
66#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
67#define CS8900_BASE 0x19000300
68#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
69
70/*
71 * select serial console configuration
72 */
Jean-Christophe PLAGNIOL-VILLARD300f99f2009-03-30 18:58:39 +020073#define CONFIG_S3C24X0_SERIAL
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020074#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
75
76/************************************************************
77 * RTC
78 ************************************************************/
79#define CONFIG_RTC_S3C24X0 1
80
81/* allow to overwrite serial and ethaddr */
82#define CONFIG_ENV_OVERWRITE
83
84#define CONFIG_BAUDRATE 115200
85
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020086
Jon Loeliger866e3082007-07-04 22:30:58 -050087/*
Jon Loeliger079a1362007-07-10 10:12:10 -050088 * BOOTP options
89 */
90#define CONFIG_BOOTP_BOOTFILESIZE
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94
95
96/*
Jon Loeliger866e3082007-07-04 22:30:58 -050097 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_ASKENV
102#define CONFIG_CMD_CACHE
103#define CONFIG_CMD_DATE
104#define CONFIG_CMD_DHCP
105#define CONFIG_CMD_ELF
106#define CONFIG_CMD_PING
Jon Loeliger866e3082007-07-04 22:30:58 -0500107
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200108
109#define CONFIG_BOOTDELAY 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200110#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
111 "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
112 "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200113#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
114#define CONFIG_NETMASK 255.255.255.0
115#define CONFIG_IPADDR 192.168.0.69
116#define CONFIG_SERVERIP 192.168.0.1
117/*#define CONFIG_BOOTFILE "elinos-lart" */
118#define CONFIG_BOOTCOMMAND "dhcp; bootm"
119
Jon Loeliger866e3082007-07-04 22:30:58 -0500120#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200121#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
122/* what's this ? it's not used anywhere */
123#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
124#endif
125
126/*
127 * Miscellaneous configurable options
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
130#define CONFIG_SYS_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
131#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200140
141/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
142/* it to wrap 100 times (total 1562500) to get 1 sec. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HZ 1562500
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200144
145/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200147
148/*-----------------------------------------------------------------------
149 * Stack sizes
150 *
151 * The stack sizes are set up in start.S using the settings below
152 */
153#define CONFIG_STACKSIZE (128*1024) /* regular stack */
154#ifdef CONFIG_USE_IRQ
155#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
156#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
157#endif
158
159/*-----------------------------------------------------------------------
160 * Physical Memory Map
161 */
162#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
163#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
164#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
165
166#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200169
170/*-----------------------------------------------------------------------
171 * FLASH and environment organization
172 */
173/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
174
175#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200178
179#ifdef CONFIG_AMD_LV800
180#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
182#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200183#endif
184
185#ifdef CONFIG_AMD_LV400
186#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
188#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200189#endif
190
191/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
193#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200194
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200195#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200196#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200197
198/*-----------------------------------------------------------------------
199 * NAND flash settings
200 */
Jon Loeliger866e3082007-07-04 22:30:58 -0500201#if defined(CONFIG_CMD_NAND)
Jean-Christophe PLAGNIOL-VILLARDb3f66b02009-03-30 18:58:40 +0200202#define CONFIG_NAND_S3C2410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200204#define SECTORSIZE 512
205
206#define ADDR_COLUMN 1
207#define ADDR_PAGE 2
208#define ADDR_COLUMN_PAGE 3
209
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200210#define NAND_ChipID_UNKNOWN 0x00
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200211#define NAND_MAX_FLOORS 1
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200212
213#define NAND_WAIT_READY(nand) NF_WaitRB()
214#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
215#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
216#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
217#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
218#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
219#define WRITE_NAND(d, adr) NF_Write(d)
220#define READ_NAND(adr) NF_Read()
221/* the following functions are NOP's because S3C24X0 handles this in hardware */
222#define NAND_CTL_CLRALE(nandptr)
223#define NAND_CTL_SETALE(nandptr)
224#define NAND_CTL_CLRCLE(nandptr)
225#define NAND_CTL_SETCLE(nandptr)
226/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
Jon Loeliger866e3082007-07-04 22:30:58 -0500227#endif /* CONFIG_CMD_NAND */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200228
229#define CONFIG_SETUP_MEMORY_TAGS
230#define CONFIG_INITRD_TAG
231#define CONFIG_CMDLINE_TAG
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_HUSH_PARSER
234#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200235
236#define CONFIG_CMDLINE_EDITING
237
238#ifdef CONFIG_CMDLINE_EDITING
239#undef CONFIG_AUTO_COMPLETE
240#else
241#define CONFIG_AUTO_COMPLETE
242#endif
243
244#endif /* __CONFIG_H */