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York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
10#define CONFIG_SYS_GENERIC_BOARD
11
12#define CONFIG_REMAKE_ELF
13#define CONFIG_FSL_LSCH3
14#define CONFIG_LS2085A
15#define CONFIG_GICV3
Bhupesh Sharma9c66ce62015-01-06 13:11:21 -080016#define CONFIG_FSL_TZPC_BP147
York Sunf749db32014-06-23 15:15:56 -070017
Bhupesh Sharma1b1069c2015-01-23 15:50:05 +053018/* Errata fixes */
19#define CONFIG_ARM_ERRATA_828024
20#define CONFIG_ARM_ERRATA_826974
21
Stuart Yoder39da6442015-07-02 11:29:02 +053022#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
Minghuan Lian31d34c62015-03-20 19:28:16 -070023#include <asm/arch-fsl-lsch3/config.h>
24#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
25#define CONFIG_SYS_HAS_SERDES
26#endif
27
Bhupesh Sharma422cb082015-03-19 09:20:43 -070028/* We need architecture specific misc initializations */
29#define CONFIG_ARCH_MISC_INIT
30
York Sunf749db32014-06-23 15:15:56 -070031/* Link Definitions */
Scott Woodb2d5ac52015-03-24 13:25:02 -070032#ifdef CONFIG_SPL
33#define CONFIG_SYS_TEXT_BASE 0x80400000
34#else
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070035#define CONFIG_SYS_TEXT_BASE 0x30100000
Scott Woodb2d5ac52015-03-24 13:25:02 -070036#endif
York Sunf749db32014-06-23 15:15:56 -070037
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053038#ifdef CONFIG_EMU
York Sunf749db32014-06-23 15:15:56 -070039#define CONFIG_SYS_NO_FLASH
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053040#endif
York Sunf749db32014-06-23 15:15:56 -070041
42#define CONFIG_SUPPORT_RAW_INITRD
43
44#define CONFIG_SKIP_LOWLEVEL_INIT
45#define CONFIG_BOARD_EARLY_INIT_F 1
46
York Sunf749db32014-06-23 15:15:56 -070047/* Flat Device Tree Definitions */
48#define CONFIG_OF_LIBFDT
49#define CONFIG_OF_BOARD_SETUP
50
51/* new uImage format support */
52#define CONFIG_FIT
53#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
54
Scott Woodb2d5ac52015-03-24 13:25:02 -070055#ifndef CONFIG_SPL
York Sunf749db32014-06-23 15:15:56 -070056#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Scott Woodb2d5ac52015-03-24 13:25:02 -070057#endif
York Sunf749db32014-06-23 15:15:56 -070058#ifndef CONFIG_SYS_FSL_DDR4
59#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
60#define CONFIG_SYS_DDR_RAW_TIMING
61#endif
York Sunf749db32014-06-23 15:15:56 -070062
63#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
64
York Sunf749db32014-06-23 15:15:56 -070065#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
66#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
67#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
68#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070069#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
70
York Sun8bfa3012014-09-08 12:20:01 -070071/*
72 * SMP Definitinos
73 */
74#define CPU_RELEASE_ADDR secondary_boot_func
75
York Sund9c68b12014-08-13 10:21:05 -070076#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
77#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
78/*
79 * DDR controller use 0 as the base address for binding.
80 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
81 */
82#define CONFIG_SYS_DP_DDR_BASE_PHY 0
83#define CONFIG_DP_DDR_CTRL 2
84#define CONFIG_DP_DDR_NUM_CTRLS 1
York Sunf749db32014-06-23 15:15:56 -070085
86/* Generic Timer Definitions */
York Sun207774b2015-03-20 19:28:08 -070087/*
88 * This is not an accurate number. It is used in start.S. The frequency
89 * will be udpated later when get_bus_freq(0) is available.
90 */
91#define COUNTER_FREQUENCY 25000000 /* 25MHz */
York Sunf749db32014-06-23 15:15:56 -070092
93/* Size of malloc() pool */
Prabhakar Kushwahaaa66acb2015-03-19 09:20:47 -070094#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
York Sunf749db32014-06-23 15:15:56 -070095
96/* I2C */
97#define CONFIG_CMD_I2C
98#define CONFIG_SYS_I2C
99#define CONFIG_SYS_I2C_MXC
York Sunf8cb1012015-03-20 10:20:40 -0700100#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
101#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
York Sunf749db32014-06-23 15:15:56 -0700102
103/* Serial Port */
York Sun7288c2c2015-03-20 19:28:23 -0700104#define CONFIG_CONS_INDEX 1
York Sunf749db32014-06-23 15:15:56 -0700105#define CONFIG_SYS_NS16550
106#define CONFIG_SYS_NS16550_SERIAL
107#define CONFIG_SYS_NS16550_REG_SIZE 1
108#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
109
110#define CONFIG_BAUDRATE 115200
111#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
112
113/* IFC */
114#define CONFIG_FSL_IFC
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700115
York Sunf749db32014-06-23 15:15:56 -0700116/*
York Sun7288c2c2015-03-20 19:28:23 -0700117 * During booting, IFC is mapped at the region of 0x30000000.
118 * But this region is limited to 256MB. To accommodate NOR, promjet
119 * and FPGA. This region is divided as below:
120 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
121 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
122 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
123 *
124 * To accommodate bigger NOR flash and other devices, we will map IFC
125 * chip selects to as below:
126 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
127 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
128 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
129 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
130 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
131 *
132 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sunf749db32014-06-23 15:15:56 -0700133 * CONFIG_SYS_FLASH_BASE has the final address (core view)
134 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
135 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
136 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
137 */
York Sun7288c2c2015-03-20 19:28:23 -0700138
York Sunf749db32014-06-23 15:15:56 -0700139#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
140#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
141#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
142
York Sun7288c2c2015-03-20 19:28:23 -0700143#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
144#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
145
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530146#ifndef CONFIG_SYS_NO_FLASH
147#define CONFIG_FLASH_CFI_DRIVER
148#define CONFIG_SYS_FLASH_CFI
149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
150#define CONFIG_SYS_FLASH_QUIET_TEST
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530151#endif
152
York Sun7288c2c2015-03-20 19:28:23 -0700153#ifndef __ASSEMBLY__
154unsigned long long get_qixis_addr(void);
155#endif
156#define QIXIS_BASE get_qixis_addr()
157#define QIXIS_BASE_PHYS 0x20000000
158#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lu8b064602015-03-20 19:28:31 -0700159#define QIXIS_STAT_PRES1 0xb
160#define QIXIS_SDID_MASK 0x07
161#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun7288c2c2015-03-20 19:28:23 -0700162
163#define CONFIG_SYS_NAND_BASE 0x530000000ULL
164#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530165
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700166/* Debug Server firmware */
Stuart Yoderb0ba9d42015-05-28 14:54:15 +0530167#define CONFIG_FSL_DEBUG_SERVER
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700168/* 2 sec timeout */
169#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
170
York Sunf749db32014-06-23 15:15:56 -0700171/* MC firmware */
172#define CONFIG_FSL_MC_ENET
York Sunf749db32014-06-23 15:15:56 -0700173/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Rivera125e2bc2015-03-20 19:28:18 -0700174#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
175#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
176#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
177#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
J. German Riverac1000c12015-07-02 11:28:58 +0530178#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
179#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sunf749db32014-06-23 15:15:56 -0700180
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530181/*
182 * Carve out a DDR region which will not be used by u-boot/Linux
183 *
184 * It will be used by MC and Debug Server. The MC region must be
185 * 512MB aligned, so the min size to hide is 512MB.
186 */
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700187#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530188#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
189#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
190#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700191#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
York Sunf749db32014-06-23 15:15:56 -0700192#endif
193
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700194/* PCIe */
195#define CONFIG_PCIE1 /* PCIE controler 1 */
196#define CONFIG_PCIE2 /* PCIE controler 2 */
197#define CONFIG_PCIE3 /* PCIE controler 3 */
198#define CONFIG_PCIE4 /* PCIE controler 4 */
Prabhakar Kushwaha252b17e2015-05-28 14:53:58 +0530199#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
200#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700201
202#define CONFIG_SYS_PCI_64BIT
203
204#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
205#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
206#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
207#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
208
209#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
210#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
211#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
212
213#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
214#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
215#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
216
York Sunf749db32014-06-23 15:15:56 -0700217/* Command line configuration */
218#define CONFIG_CMD_CACHE
York Sunf749db32014-06-23 15:15:56 -0700219#define CONFIG_CMD_DHCP
220#define CONFIG_CMD_ENV
Prabhakar Kushwaha778145a2015-08-07 10:24:30 +0530221#define CONFIG_CMD_GREPENV
York Sunf749db32014-06-23 15:15:56 -0700222#define CONFIG_CMD_MII
York Sunf749db32014-06-23 15:15:56 -0700223#define CONFIG_CMD_PING
York Sunf749db32014-06-23 15:15:56 -0700224
225/* Miscellaneous configurable options */
226#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
York Sun8bfa3012014-09-08 12:20:01 -0700227#define CONFIG_ARCH_EARLY_INIT_R
York Sunf749db32014-06-23 15:15:56 -0700228
229/* Physical Memory Map */
230/* fixme: these need to be checked against the board */
231#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sunf749db32014-06-23 15:15:56 -0700232
York Sund9c68b12014-08-13 10:21:05 -0700233#define CONFIG_NR_DRAM_BANKS 3
York Sunf749db32014-06-23 15:15:56 -0700234
York Sunf749db32014-06-23 15:15:56 -0700235#define CONFIG_HWCONFIG
236#define HWCONFIG_BUFFER_SIZE 128
237
238#define CONFIG_DISPLAY_CPUINFO
239
240/* Initial environment variables */
241#define CONFIG_EXTRA_ENV_SETTINGS \
242 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
243 "loadaddr=0x80100000\0" \
244 "kernel_addr=0x100000\0" \
245 "ramdisk_addr=0x800000\0" \
246 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700247 "fdt_high=0xa0000000\0" \
York Sunf749db32014-06-23 15:15:56 -0700248 "initrd_high=0xffffffffffffffff\0" \
249 "kernel_start=0x581200000\0" \
Stuart Yoder052ddd52015-01-06 13:18:57 -0800250 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha97421bd2015-07-01 16:28:22 +0530251 "kernel_size=0x2800000\0" \
York Sunf749db32014-06-23 15:15:56 -0700252 "console=ttyAMA0,38400n8\0"
253
Prabhakar Kushwaha56cd0762015-08-02 09:11:44 +0530254#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
255 "earlycon=uart8250,mmio,0x21c0500,115200 " \
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530256 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
257 " hugepagesz=2m hugepages=16"
York Sunf749db32014-06-23 15:15:56 -0700258#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
259 "$kernel_size && bootm $kernel_load"
York Sun7288c2c2015-03-20 19:28:23 -0700260#define CONFIG_BOOTDELAY 10
York Sunf749db32014-06-23 15:15:56 -0700261
York Sunf749db32014-06-23 15:15:56 -0700262/* Monitor Command Prompt */
263#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
York Sunf749db32014-06-23 15:15:56 -0700264#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
265 sizeof(CONFIG_SYS_PROMPT) + 16)
266#define CONFIG_SYS_HUSH_PARSER
267#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
268#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
269#define CONFIG_SYS_LONGHELP
270#define CONFIG_CMDLINE_EDITING 1
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700271#define CONFIG_AUTO_COMPLETE
York Sunf749db32014-06-23 15:15:56 -0700272#define CONFIG_SYS_MAXARGS 64 /* max command args */
273
274#ifndef __ASSEMBLY__
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700275unsigned long get_dram_size_to_hide(void);
York Sunf749db32014-06-23 15:15:56 -0700276#endif
277
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700278#define CONFIG_PANIC_HANG /* do not reset board on panic */
279
Scott Woodb2d5ac52015-03-24 13:25:02 -0700280#define CONFIG_SPL_BSS_START_ADDR 0x80100000
281#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
282#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
283#define CONFIG_SPL_ENV_SUPPORT
284#define CONFIG_SPL_FRAMEWORK
285#define CONFIG_SPL_I2C_SUPPORT
286#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
287#define CONFIG_SPL_LIBCOMMON_SUPPORT
288#define CONFIG_SPL_LIBGENERIC_SUPPORT
289#define CONFIG_SPL_MAX_SIZE 0x16000
290#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
291#define CONFIG_SPL_NAND_SUPPORT
292#define CONFIG_SPL_SERIAL_SUPPORT
293#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
294#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
295#define CONFIG_SPL_TEXT_BASE 0x1800a000
296
297#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
298#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
299#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
300#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
301#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
302
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530303#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
304
305
York Sunf749db32014-06-23 15:15:56 -0700306#endif /* __LS2_COMMON_H */