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Stefano Babic8edcde52010-01-20 18:19:10 +01001/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic8edcde52010-01-20 18:19:10 +01006 */
7
8#ifndef _IMXIMAGE_H_
9#define _IMXIMAGE_H_
10
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000011#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
12#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
Stefano Babic8edcde52010-01-20 18:19:10 +010013#define APP_CODE_BARKER 0xB1
14#define DCD_BARKER 0xB17219E9
Stefano Babic8edcde52010-01-20 18:19:10 +010015
Marek Vasut6cb83822013-04-25 10:16:02 +000016/*
17 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
18 * imx-common/imximage.cfg because tools/imximage.c can not
19 * cross-include headers from arch/arm/ and vice-versa.
20 */
Stefano Babic8edcde52010-01-20 18:19:10 +010021#define CMD_DATA_STR "DATA"
Stefano Babic377e3672013-06-26 23:50:06 +020022
23/* Initial Vector Table Offset */
Dirk Behme49d3e272012-02-22 22:50:19 +000024#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
Stefano Babic8edcde52010-01-20 18:19:10 +010025#define FLASH_OFFSET_STANDARD 0x400
26#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
27#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
28#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
29#define FLASH_OFFSET_ONENAND 0x100
Dirk Behme19b409c2012-01-11 23:28:31 +000030#define FLASH_OFFSET_NOR 0x1000
31#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
Stefano Babic8edcde52010-01-20 18:19:10 +010032
Stefano Babic377e3672013-06-26 23:50:06 +020033/* Initial Load Region Size */
34#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
35#define FLASH_LOADSIZE_STANDARD 0x1000
36#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
37#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
38#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
39#define FLASH_LOADSIZE_ONENAND 0x400
40#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
41#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
42
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000043#define IVT_HEADER_TAG 0xD1
44#define IVT_VERSION 0x40
45#define DCD_HEADER_TAG 0xD2
46#define DCD_COMMAND_TAG 0xCC
47#define DCD_VERSION 0x40
48#define DCD_COMMAND_PARAM 0x4
49
Stefano Babic8edcde52010-01-20 18:19:10 +010050enum imximage_cmd {
51 CMD_INVALID,
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000052 CMD_IMAGE_VERSION,
Stefano Babic8edcde52010-01-20 18:19:10 +010053 CMD_BOOT_FROM,
Marek Vasut6cb83822013-04-25 10:16:02 +000054 CMD_BOOT_OFFSET,
Stefano Babic0187c982013-06-27 11:42:38 +020055 CMD_DATA,
56 CMD_CSF,
Stefano Babic8edcde52010-01-20 18:19:10 +010057};
58
59enum imximage_fld_types {
60 CFG_INVALID = -1,
61 CFG_COMMAND,
62 CFG_REG_SIZE,
63 CFG_REG_ADDRESS,
64 CFG_REG_VALUE
65};
66
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000067enum imximage_version {
68 IMXIMAGE_VER_INVALID = -1,
69 IMXIMAGE_V1 = 1,
70 IMXIMAGE_V2
71};
Stefano Babic8edcde52010-01-20 18:19:10 +010072
73typedef struct {
74 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
75 uint32_t addr; /* Address to write to */
76 uint32_t value; /* Data to write */
77} dcd_type_addr_data_t;
78
79typedef struct {
80 uint32_t barker; /* Barker for sanity check */
81 uint32_t length; /* Device configuration length (without preamble) */
82} dcd_preamble_t;
83
84typedef struct {
85 dcd_preamble_t preamble;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000086 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
87} dcd_v1_t;
Stefano Babic8edcde52010-01-20 18:19:10 +010088
89typedef struct {
90 uint32_t app_code_jump_vector;
91 uint32_t app_code_barker;
92 uint32_t app_code_csf;
93 uint32_t dcd_ptr_ptr;
Stefano Babic5b28e912010-02-05 15:16:02 +010094 uint32_t super_root_key;
Stefano Babic8edcde52010-01-20 18:19:10 +010095 uint32_t dcd_ptr;
96 uint32_t app_dest_ptr;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000097} flash_header_v1_t;
Stefano Babic8edcde52010-01-20 18:19:10 +010098
99typedef struct {
100 uint32_t length; /* Length of data to be read from flash */
101} flash_cfg_parms_t;
102
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000103typedef struct {
104 flash_header_v1_t fhdr;
105 dcd_v1_t dcd_table;
Stefano Babic8edcde52010-01-20 18:19:10 +0100106 flash_cfg_parms_t ext_header;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000107} imx_header_v1_t;
108
109typedef struct {
110 uint32_t addr;
111 uint32_t value;
112} dcd_addr_data_t;
113
114typedef struct {
115 uint8_t tag;
116 uint16_t length;
117 uint8_t version;
118} __attribute__((packed)) ivt_header_t;
119
120typedef struct {
121 uint8_t tag;
122 uint16_t length;
123 uint8_t param;
124} __attribute__((packed)) write_dcd_command_t;
125
126typedef struct {
127 ivt_header_t header;
128 write_dcd_command_t write_dcd_command;
129 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
130} dcd_v2_t;
131
132typedef struct {
133 uint32_t start;
134 uint32_t size;
135 uint32_t plugin;
136} boot_data_t;
137
138typedef struct {
139 ivt_header_t header;
140 uint32_t entry;
141 uint32_t reserved1;
142 uint32_t dcd_ptr;
143 uint32_t boot_data_ptr;
144 uint32_t self;
145 uint32_t csf;
146 uint32_t reserved2;
147} flash_header_v2_t;
148
149typedef struct {
150 flash_header_v2_t fhdr;
151 boot_data_t boot_data;
152 dcd_v2_t dcd_table;
153} imx_header_v2_t;
154
Marek Vasut895d9962013-04-21 05:52:22 +0000155/* The header must be aligned to 4k on MX53 for NAND boot */
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000156struct imx_header {
157 union {
158 imx_header_v1_t hdr_v1;
159 imx_header_v2_t hdr_v2;
160 } header;
Stefano Babic377e3672013-06-26 23:50:06 +0200161};
Stefano Babic8edcde52010-01-20 18:19:10 +0100162
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000163typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
164 char *name, int lineno,
165 int fld, uint32_t value,
166 uint32_t off);
167
168typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
169 uint32_t dcd_len,
170 char *name, int lineno);
171
Troy Kiskyad0826d2012-10-03 15:47:08 +0000172typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
173 uint32_t entry_point, uint32_t flash_offset);
Stefano Babic8edcde52010-01-20 18:19:10 +0100174
175#endif /* _IMXIMAGE_H_ */