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Jon Loeliger5c9efb32006-04-27 10:15:16 -05001/*
Kumar Gala1b77ca82011-01-04 17:45:13 -06002 * Copyright 2006, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c9efb32006-04-27 10:15:16 -05003 *
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05007 */
8
9/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -050010 * MPC8641HPCN board configuration file
Jon Loeligerdebb7352006-04-26 17:58:56 -050011 *
12 * Make sure you change the MAC address and other network params first,
13 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
14 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/* High Level Configuration Options */
20#define CONFIG_MPC86xx 1 /* MPC86xx */
21#define CONFIG_MPC8641 1 /* MPC8641 specific */
22#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050023#define CONFIG_MP 1 /* support multiple processors */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020024#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
Becky Bruce3111d322008-11-06 17:37:35 -060025/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
Becky Bruced591a802009-02-03 18:10:54 -060026#define CONFIG_ADDR_MAP 1 /* Use addr map */
Jon Loeligerdebb7352006-04-26 17:58:56 -050027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028/*
29 * default CCSRBAR is at 0xff700000
30 * assume U-Boot is less than 0.5MB
31 */
32#define CONFIG_SYS_TEXT_BASE 0xeff00000
33
Jon Loeligerdebb7352006-04-26 17:58:56 -050034#ifdef RUN_DIAG
Becky Bruce6bf98b12008-11-05 14:55:33 -060035#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -050036#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050037
Becky Bruceaf5d1002008-10-31 17:14:14 -050038/*
Becky Bruce1266df82008-11-03 15:44:01 -060039 * virtual address to be used for temporary mappings. There
40 * should be 128k free at this VA.
41 */
42#define CONFIG_SYS_SCRATCH_VA 0xe0000000
43
Kumar Gala1b77ca82011-01-04 17:45:13 -060044#define CONFIG_SYS_SRIO
45#define CONFIG_SRIO1 /* SRIO port 1 */
Becky Bruceaf5d1002008-10-31 17:14:14 -050046
Ed Swarthout63cec582007-08-02 14:09:49 -050047#define CONFIG_PCI 1 /* Enable PCI/PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050048#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
49#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
Ed Swarthout63cec582007-08-02 14:09:49 -050050#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050051#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce4933b912008-01-23 16:31:01 -060052#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
Jon Loeliger5c9efb32006-04-27 10:15:16 -050053
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerdebb7352006-04-26 17:58:56 -050055#define CONFIG_ENV_OVERWRITE
Jon Loeliger5c9efb32006-04-27 10:15:16 -050056
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050057#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050058#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
Becky Bruced591a802009-02-03 18:10:54 -060059#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
Jon Loeligerdebb7352006-04-26 17:58:56 -050060
Wolfgang Denk53677ef2008-05-20 16:00:29 +020061#define CONFIG_ALTIVEC 1
Jon Loeligerdebb7352006-04-26 17:58:56 -050062
Jon Loeliger5c9efb32006-04-27 10:15:16 -050063/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050064 * L2CR setup -- make sure this is right for your board!
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -050067#define L2_INIT 0
68#define L2_ENABLE (L2CR_L2E)
69
70#ifndef CONFIG_SYS_CLK_FREQ
Ed Swarthout63cec582007-08-02 14:09:49 -050071#ifndef __ASSEMBLY__
72extern unsigned long get_board_sys_clk(unsigned long dummy);
73#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020074#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -050075#endif
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
78#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerdebb7352006-04-26 17:58:56 -050079
Jon Loeligerdebb7352006-04-26 17:58:56 -050080/*
Becky Bruce3111d322008-11-06 17:37:35 -060081 * With the exception of PCI Memory and Rapid IO, most devices will simply
82 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
83 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
84 */
85#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -050086#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
Becky Bruce3111d322008-11-06 17:37:35 -060087#else
Becky Bruce1605cc92011-10-03 19:10:51 -050088#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -060089#endif
90
91/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050092 * Base addresses -- Note these are effective addresses where the
93 * actual resources get mapped (not physical addresses)
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Becky Brucec759a012008-11-06 17:36:04 -060096#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerdebb7352006-04-26 17:58:56 -050098
Becky Bruce3111d322008-11-06 17:37:35 -060099/* Physical addresses */
100#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Becky Bruce1605cc92011-10-03 19:10:51 -0500101#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
102#define CONFIG_SYS_CCSRBAR_PHYS \
103 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
104 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600105
york076bff82010-07-02 22:25:52 +0000106#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
107
Jon Loeligerdebb7352006-04-26 17:58:56 -0500108/*
109 * DDR Setup
110 */
Kumar Gala6a8e5692008-08-26 15:01:35 -0500111#define CONFIG_FSL_DDR2
112#undef CONFIG_FSL_DDR_INTERACTIVE
113#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
114#define CONFIG_DDR_SPD
115
116#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
117#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
120#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600121#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jin Zhengxiongfcb28e72006-07-13 10:35:10 -0500122#define CONFIG_VERY_BIG_RAM
Jon Loeligerdebb7352006-04-26 17:58:56 -0500123
Kumar Gala6a8e5692008-08-26 15:01:35 -0500124#define CONFIG_NUM_DDR_CONTROLLERS 2
125#define CONFIG_DIMM_SLOTS_PER_CTLR 2
126#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500127
Kumar Gala6a8e5692008-08-26 15:01:35 -0500128/*
129 * I2C addresses of SPD EEPROMs
130 */
131#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
132#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
133#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
134#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500135
Jon Loeligerdebb7352006-04-26 17:58:56 -0500136
Kumar Gala6a8e5692008-08-26 15:01:35 -0500137/*
138 * These are used when DDR doesn't use SPD.
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
141#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
142#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
143#define CONFIG_SYS_DDR_TIMING_3 0x00000000
144#define CONFIG_SYS_DDR_TIMING_0 0x00260802
145#define CONFIG_SYS_DDR_TIMING_1 0x39357322
146#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
147#define CONFIG_SYS_DDR_MODE_1 0x00480432
148#define CONFIG_SYS_DDR_MODE_2 0x00000000
149#define CONFIG_SYS_DDR_INTERVAL 0x06090100
150#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
151#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
152#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
153#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
154#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
155#define CONFIG_SYS_DDR_CONTROL2 0x04400000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500156
Jon Loeligerad8f8682008-01-15 13:42:41 -0600157#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200159#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
161#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500162
Becky Brucec759a012008-11-06 17:36:04 -0600163#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
Becky Bruce1605cc92011-10-03 19:10:51 -0500164#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
165#define CONFIG_SYS_FLASH_BASE_PHYS \
166 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
167 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600168
Becky Bruceb81b7732009-02-02 16:34:52 -0600169#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500170
Becky Bruce3111d322008-11-06 17:37:35 -0600171#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
172 | 0x00001001) /* port size 16bit */
173#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500174
Becky Bruce3111d322008-11-06 17:37:35 -0600175#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
176 | 0x00001001) /* port size 16bit */
177#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500178
Becky Bruce3111d322008-11-06 17:37:35 -0600179#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
180 | 0x00000801) /* port size 8bit */
181#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500182
Becky Brucec759a012008-11-06 17:36:04 -0600183/*
184 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
185 * The PIXIS and CF by themselves aren't large enough to take up the 128k
186 * required for the smallest BAT mapping, so there's a 64k hole.
187 */
188#define CONFIG_SYS_LBC_BASE 0xffde0000
Becky Bruce1605cc92011-10-03 19:10:51 -0500189#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500190
Kim Phillips7608d752007-08-21 17:00:17 -0500191#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Becky Brucec759a012008-11-06 17:36:04 -0600192#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
Becky Bruce1605cc92011-10-03 19:10:51 -0500193#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
194#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
195 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Brucec759a012008-11-06 17:36:04 -0600196#define PIXIS_SIZE 0x00008000 /* 32k */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500197#define PIXIS_ID 0x0 /* Board ID at offset 0 */
198#define PIXIS_VER 0x1 /* Board version at offset 1 */
199#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
200#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
201#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
202#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
203#define PIXIS_VCTL 0x10 /* VELA Control Register */
204#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
205#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
206#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala9af9c6b2009-07-15 13:45:00 -0500207#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
208#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500209#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
210#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
211#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
212#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500214
Becky Bruceb5431562008-10-31 17:13:49 -0500215/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
Becky Brucec759a012008-11-06 17:36:04 -0600216#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
Becky Bruce3111d322008-11-06 17:37:35 -0600217#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
Becky Bruceb5431562008-10-31 17:13:49 -0500218
Becky Bruce170deac2008-11-05 14:55:32 -0600219#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#undef CONFIG_SYS_FLASH_CHECKSUM
223#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
224#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600226#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500227
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200228#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_CFI
230#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
233#define CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500234#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#undef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500236#endif
237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#if defined(CONFIG_SYS_RAMBOOT)
Jin Zhengxiong-R64188fa7db9c2006-06-27 18:11:54 +0800239#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500241#endif
242
243#undef CONFIG_CLOCKS_IN_MHZ
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_INIT_RAM_LOCK 1
246#ifndef CONFIG_SYS_INIT_RAM_LOCK
247#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500248#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500250#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200251#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500252
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerdebb7352006-04-26 17:58:56 -0500255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
257#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500258
259/* Serial Port */
260#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_NS16550
262#define CONFIG_SYS_NS16550_SERIAL
263#define CONFIG_SYS_NS16550_REG_SIZE 1
264#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerdebb7352006-04-26 17:58:56 -0500267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
270#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500271
272/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_HUSH_PARSER
Jon Loeligerdebb7352006-04-26 17:58:56 -0500274
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500275/*
276 * Pass open firmware flat tree to kernel
277 */
Jon Loeligerea9f7392007-11-28 14:47:18 -0600278#define CONFIG_OF_LIBFDT 1
279#define CONFIG_OF_BOARD_SETUP 1
280#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500281
Jon Loeliger586d1d52006-05-19 13:22:44 -0500282/*
283 * I2C
284 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200285#define CONFIG_SYS_I2C
286#define CONFIG_SYS_I2C_FSL
287#define CONFIG_SYS_FSL_I2C_SPEED 400000
288#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
289#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
290#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500291
Jon Loeliger586d1d52006-05-19 13:22:44 -0500292/*
293 * RapidIO MMU
294 */
Kumar Gala1b77ca82011-01-04 17:45:13 -0600295#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
Becky Bruce3111d322008-11-06 17:37:35 -0600296#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500297#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
298#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600299#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500300#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
301#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600302#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500303#define CONFIG_SYS_SRIO1_MEM_PHYS \
304 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
305 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600306#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500307
308/*
309 * General PCI
310 * Addresses are mapped 1-1.
311 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600312
Kumar Gala64e55d52010-12-17 10:47:36 -0600313#define CONFIG_SYS_PCIE1_NAME "ULI"
Kumar Gala46f3e382010-07-09 00:02:34 -0500314#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Becky Bruce3111d322008-11-06 17:37:35 -0600315#ifdef CONFIG_PHYS_64BIT
Kumar Gala46f3e382010-07-09 00:02:34 -0500316#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Becky Bruce1605cc92011-10-03 19:10:51 -0500317#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
318#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600319#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500320#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
Becky Bruce1605cc92011-10-03 19:10:51 -0500321#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
322#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600323#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500324#define CONFIG_SYS_PCIE1_MEM_PHYS \
325 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
326 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500327#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
328#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
329#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Becky Bruce1605cc92011-10-03 19:10:51 -0500330#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
331#define CONFIG_SYS_PCIE1_IO_PHYS \
332 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
333 CONFIG_SYS_PHYS_ADDR_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500334#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500335
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600336#ifdef CONFIG_PHYS_64BIT
337/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500338 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600339 * This will increase the amount of PCI address space available for
340 * for mapping RAM.
341 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500342#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600343#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500344#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
345 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600346#endif
Kumar Gala46f3e382010-07-09 00:02:34 -0500347#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
348 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500349#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
350 + CONFIG_SYS_PCIE1_MEM_SIZE)
351#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
Kumar Gala46f3e382010-07-09 00:02:34 -0500352#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
353 + CONFIG_SYS_PCIE1_MEM_SIZE)
354#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
355#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
356#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
357 + CONFIG_SYS_PCIE1_IO_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500358#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
359 + CONFIG_SYS_PCIE1_IO_SIZE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500360#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
361 + CONFIG_SYS_PCIE1_IO_SIZE)
362#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500363
Jon Loeligerdebb7352006-04-26 17:58:56 -0500364#if defined(CONFIG_PCI)
365
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200366#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500369
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200370#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500371
372#define CONFIG_RTL8139
373
Jon Loeligerdebb7352006-04-26 17:58:56 -0500374#undef CONFIG_EEPRO100
375#undef CONFIG_TULIP
376
Zhang Weia81d1c02007-06-06 10:08:14 +0200377/************************************************************
378 * USB support
379 ************************************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200380#define CONFIG_PCI_OHCI 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200381#define CONFIG_USB_OHCI_NEW 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200382#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200383#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_USB_EVENT_POLL 1
385#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
386#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
387#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200388
Jason Jin0f460a12007-07-13 12:14:58 +0800389/*PCIE video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500390#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800391
392/*PCI video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500393/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
Jason Jin0f460a12007-07-13 12:14:58 +0800394
395/* video */
396#define CONFIG_VIDEO
397
398#if defined(CONFIG_VIDEO)
399#define CONFIG_BIOSEMU
400#define CONFIG_CFB_CONSOLE
401#define CONFIG_VIDEO_SW_CURSOR
402#define CONFIG_VGA_AS_SINGLE_DEVICE
403#define CONFIG_ATI_RADEON_FB
404#define CONFIG_VIDEO_LOGO
405/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500406#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800407#endif
408
Jon Loeligerdebb7352006-04-26 17:58:56 -0500409#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500410
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800411#define CONFIG_DOS_PARTITION
412#define CONFIG_SCSI_AHCI
413
414#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500415#define CONFIG_LIBATA
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800416#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
418#define CONFIG_SYS_SCSI_MAX_LUN 1
419#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
420#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800421#endif
422
Jon Loeligerdebb7352006-04-26 17:58:56 -0500423#endif /* CONFIG_PCI */
424
Jon Loeligerdebb7352006-04-26 17:58:56 -0500425#if defined(CONFIG_TSEC_ENET)
426
Jon Loeligerdebb7352006-04-26 17:58:56 -0500427#define CONFIG_MII 1 /* MII PHY management */
428
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200429#define CONFIG_TSEC1 1
430#define CONFIG_TSEC1_NAME "eTSEC1"
431#define CONFIG_TSEC2 1
432#define CONFIG_TSEC2_NAME "eTSEC2"
433#define CONFIG_TSEC3 1
434#define CONFIG_TSEC3_NAME "eTSEC3"
435#define CONFIG_TSEC4 1
436#define CONFIG_TSEC4_NAME "eTSEC4"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500437
Jon Loeligerdebb7352006-04-26 17:58:56 -0500438#define TSEC1_PHY_ADDR 0
439#define TSEC2_PHY_ADDR 1
440#define TSEC3_PHY_ADDR 2
441#define TSEC4_PHY_ADDR 3
442#define TSEC1_PHYIDX 0
443#define TSEC2_PHYIDX 0
444#define TSEC3_PHYIDX 0
445#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500446#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
447#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
448#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
449#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500450
451#define CONFIG_ETHPRIME "eTSEC1"
452
453#endif /* CONFIG_TSEC_ENET */
454
Becky Bruce1605cc92011-10-03 19:10:51 -0500455
Becky Bruce3111d322008-11-06 17:37:35 -0600456#ifdef CONFIG_PHYS_64BIT
Becky Bruce3111d322008-11-06 17:37:35 -0600457#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
458#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
459
Becky Bruce1605cc92011-10-03 19:10:51 -0500460/* Put physical address into the BAT format */
461#define BAT_PHYS_ADDR(low, high) \
462 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
463/* Convert high/low pairs to actual 64-bit value */
464#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
465#else
466/* 32-bit systems just ignore the "high" bits */
467#define BAT_PHYS_ADDR(low, high) (low)
468#define PAIRED_PHYS_TO_PHYS(low, high) (low)
469#endif
470
Jon Loeliger586d1d52006-05-19 13:22:44 -0500471/*
Becky Brucec759a012008-11-06 17:36:04 -0600472 * BAT0 DDR
Jon Loeligerdebb7352006-04-26 17:58:56 -0500473 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Timur Tabi9ff32d82010-03-29 12:51:07 -0500475#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500476
Jon Loeliger586d1d52006-05-19 13:22:44 -0500477/*
Becky Brucec759a012008-11-06 17:36:04 -0600478 * BAT1 LBC (PIXIS/CF)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500479 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500480#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
481 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600482 | BATL_PP_RW | BATL_CACHEINHIBIT | \
483 BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600484#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
485 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500486#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
487 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600488 | BATL_PP_RW | BATL_MEMCOHERENCE)
Becky Brucec759a012008-11-06 17:36:04 -0600489#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500490
491/* if CONFIG_PCI:
Kumar Gala46f3e382010-07-09 00:02:34 -0500492 * BAT2 PCIE1 and PCIE1 MEM
Becky Bruceaf5d1002008-10-31 17:14:14 -0500493 * if CONFIG_RIO
Becky Brucec759a012008-11-06 17:36:04 -0600494 * BAT2 Rapidio Memory
Jon Loeligerdebb7352006-04-26 17:58:56 -0500495 */
Becky Bruceaf5d1002008-10-31 17:14:14 -0500496#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000497#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce1605cc92011-10-03 19:10:51 -0500498#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
499 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600500 | BATL_PP_RW | BATL_CACHEINHIBIT \
501 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500502#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
Becky Bruceaf5d1002008-10-31 17:14:14 -0500503 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500504#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
505 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600506 | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500507#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
508#else /* CONFIG_RIO */
Becky Bruce1605cc92011-10-03 19:10:51 -0500509#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
510 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600511 | BATL_PP_RW | BATL_CACHEINHIBIT | \
512 BATL_GUARDEDSTORAGE)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600513#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
Becky Bruce3111d322008-11-06 17:37:35 -0600514 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500515#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
516 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600517 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500519#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500520
Jon Loeliger586d1d52006-05-19 13:22:44 -0500521/*
Becky Brucec759a012008-11-06 17:36:04 -0600522 * BAT3 CCSR Space
Jon Loeligerdebb7352006-04-26 17:58:56 -0500523 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500524#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
525 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600526 | BATL_PP_RW | BATL_CACHEINHIBIT \
527 | BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600528#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
529 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500530#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
531 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600532 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500534
Becky Bruce3111d322008-11-06 17:37:35 -0600535#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
536#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
537 | BATL_PP_RW | BATL_CACHEINHIBIT \
538 | BATL_GUARDEDSTORAGE)
539#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
540 | BATU_BL_1M | BATU_VS | BATU_VP)
541#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
542 | BATL_PP_RW | BATL_CACHEINHIBIT)
543#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
544#endif
545
Jon Loeliger586d1d52006-05-19 13:22:44 -0500546/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500547 * BAT4 PCIE1_IO and PCIE2_IO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500548 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500549#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
550 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600551 | BATL_PP_RW | BATL_CACHEINHIBIT \
552 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500553#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
Becky Brucec759a012008-11-06 17:36:04 -0600554 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500555#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
556 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600557 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500559
Jon Loeliger586d1d52006-05-19 13:22:44 -0500560/*
Becky Brucec759a012008-11-06 17:36:04 -0600561 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500562 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
564#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
565#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
566#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500567
Jon Loeliger586d1d52006-05-19 13:22:44 -0500568/*
Becky Brucec759a012008-11-06 17:36:04 -0600569 * BAT6 FLASH
Jon Loeligerdebb7352006-04-26 17:58:56 -0500570 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500571#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
572 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600573 | BATL_PP_RW | BATL_CACHEINHIBIT \
574 | BATL_GUARDEDSTORAGE)
Becky Bruce170deac2008-11-05 14:55:32 -0600575#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
576 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500577#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
578 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600579 | BATL_PP_RW | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500581
Becky Brucebf9a8c32008-11-05 14:55:35 -0600582/* Map the last 1M of flash where we're running from reset */
583#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
584 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200585#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600586#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
587 | BATL_MEMCOHERENCE)
588#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
589
Becky Brucec759a012008-11-06 17:36:04 -0600590/*
591 * BAT7 FREE - used later for tmp mappings
592 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593#define CONFIG_SYS_DBAT7L 0x00000000
594#define CONFIG_SYS_DBAT7U 0x00000000
595#define CONFIG_SYS_IBAT7L 0x00000000
596#define CONFIG_SYS_IBAT7U 0x00000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500597
Jon Loeligerdebb7352006-04-26 17:58:56 -0500598/*
599 * Environment
600 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200602 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200604 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500605#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200606 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500608#endif
Becky Bruce0f2d6602008-11-05 14:55:31 -0600609#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500610
611#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500613
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500614
615/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500616 * BOOTP options
617 */
618#define CONFIG_BOOTP_BOOTFILESIZE
619#define CONFIG_BOOTP_BOOTPATH
620#define CONFIG_BOOTP_GATEWAY
621#define CONFIG_BOOTP_HOSTNAME
622
623
624/*
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500625 * Command line configuration.
626 */
627#include <config_cmd_default.h>
628
629#define CONFIG_CMD_PING
630#define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600631#define CONFIG_CMD_REGINFO
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500632
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500634 #undef CONFIG_CMD_SAVEENV
Jon Loeligerdebb7352006-04-26 17:58:56 -0500635#endif
636
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500637#if defined(CONFIG_PCI)
638 #define CONFIG_CMD_PCI
639 #define CONFIG_CMD_SCSI
640 #define CONFIG_CMD_EXT2
Zhang Weibbf47962007-10-25 17:30:04 +0800641 #define CONFIG_CMD_USB
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500642#endif
643
Jon Loeligerdebb7352006-04-26 17:58:56 -0500644
645#undef CONFIG_WATCHDOG /* watchdog disabled */
646
647/*
648 * Miscellaneous configurable options
649 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200650#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200651#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200652#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
653#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500654
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500655#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500657#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200658 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500659#endif
660
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200661#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
662#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
663#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
664#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500665
666/*
667 * For booting Linux, the board info and command line data
668 * have to be in the first 8 MB of memory, since this is
669 * the maximum mapped by the Linux kernel during initialization.
670 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200671#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500672
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500673#if defined(CONFIG_CMD_KGDB)
674 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
675 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500676#endif
677
Jon Loeligerdebb7352006-04-26 17:58:56 -0500678/*
679 * Environment Configuration
680 */
681
682/* The mac addresses for all ethernet interface */
683#if defined(CONFIG_TSEC_ENET)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200684#define CONFIG_ETHADDR 00:E0:0C:00:00:01
Jon Loeligerdebb7352006-04-26 17:58:56 -0500685#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
686#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
687#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
688#endif
689
Andy Fleming10327dc2007-08-16 16:35:02 -0500690#define CONFIG_HAS_ETH0 1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500691#define CONFIG_HAS_ETH1 1
692#define CONFIG_HAS_ETH2 1
693#define CONFIG_HAS_ETH3 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500694
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500695#define CONFIG_IPADDR 192.168.1.100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500696
697#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000698#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000699#define CONFIG_BOOTFILE "uImage"
Ed Swarthout32922cd2007-06-05 12:30:52 -0500700#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500701
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500702#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500703#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500704#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500705
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500706/* default location for tftp and bootm */
707#define CONFIG_LOADADDR 1000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500708
709#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200710#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500711
712#define CONFIG_BAUDRATE 115200
713
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200714#define CONFIG_EXTRA_ENV_SETTINGS \
715 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200716 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200717 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200718 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
719 " +$filesize; " \
720 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
721 " +$filesize; " \
722 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
723 " $filesize; " \
724 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
725 " +$filesize; " \
726 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
727 " $filesize\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200728 "consoledev=ttyS0\0" \
729 "ramdiskaddr=2000000\0" \
730 "ramdiskfile=your.ramdisk.u-boot\0" \
731 "fdtaddr=c00000\0" \
732 "fdtfile=mpc8641_hpcn.dtb\0" \
Becky Bruce3111d322008-11-06 17:37:35 -0600733 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
734 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200735 "maxcpus=2"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500736
737
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200738#define CONFIG_NFSBOOTCOMMAND \
739 "setenv bootargs root=/dev/nfs rw " \
740 "nfsroot=$serverip:$rootpath " \
741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "tftp $loadaddr $bootfile;" \
744 "tftp $fdtaddr $fdtfile;" \
745 "bootm $loadaddr - $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500746
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200747#define CONFIG_RAMBOOTCOMMAND \
748 "setenv bootargs root=/dev/ram rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $ramdiskaddr $ramdiskfile;" \
751 "tftp $loadaddr $bootfile;" \
752 "tftp $fdtaddr $fdtfile;" \
753 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500754
755#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
756
757#endif /* __CONFIG_H */