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gerrit.cesnet.cz / github / trini / u-boot / 76db5b8f59d0c9c9eb73f1595f8fbc557e7a16eb / . / arch / arm / cpu / armv7 / omap4 / emif.c
blob: 53f60635b195b2473df814117409545f55402f8a [file] [log] [blame]
Sricharanbb772a52011-11-15 09:50:00 -0500[diff] [blame]1/*
2 * EMIF programming
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Aneesh V <aneesh@ti.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <asm/emif.h>
30#include <asm/arch/sys_proto.h>
31#include <asm/utils.h>
32
33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
35u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
Sricharanbb772a52011-11-15 09:50:00 -0500[diff] [blame]36#endif
37
38#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
39/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
40static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
41 .max_freq = 400000000,
42 .RL = 6,
43 .tRPab = 21,
44 .tRCD = 18,
45 .tWR = 15,
46 .tRASmin = 42,
47 .tRRD = 10,
48 .tWTRx2 = 15,
49 .tXSR = 140,
50 .tXPx2 = 15,
51 .tRFCab = 130,
52 .tRTPx2 = 15,
53 .tCKE = 3,
54 .tCKESR = 15,
55 .tZQCS = 90,
56 .tZQCL = 360,
57 .tZQINIT = 1000,
58 .tDQSCKMAXx2 = 11,
59 .tRASmax = 70,
60 .tFAW = 50
61};
62
63/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
64static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
65 .max_freq = 200000000,
66 .RL = 3,
67 .tRPab = 21,
68 .tRCD = 18,
69 .tWR = 15,
70 .tRASmin = 42,
71 .tRRD = 10,
72 .tWTRx2 = 20,
73 .tXSR = 140,
74 .tXPx2 = 15,
75 .tRFCab = 130,
76 .tRTPx2 = 15,
77 .tCKE = 3,
78 .tCKESR = 15,
79 .tZQCS = 90,
80 .tZQCL = 360,
81 .tZQINIT = 1000,
82 .tDQSCKMAXx2 = 11,
83 .tRASmax = 70,
84 .tFAW = 50
85};
86
87/*
88 * Min tCK values specified by JESD209-2
89 * Min tCK specifies the minimum duration of some AC timing parameters in terms
90 * of the number of cycles. If the calculated number of cycles based on the
91 * absolute time value is less than the min tCK value, min tCK value should
92 * be used instead. This typically happens at low frequencies.
93 */
94static const struct lpddr2_min_tck min_tck_jedec = {
95 .tRL = 3,
96 .tRP_AB = 3,
97 .tRCD = 3,
98 .tWR = 3,
99 .tRAS_MIN = 3,
100 .tRRD = 2,
101 .tWTR = 2,
102 .tXP = 2,
103 .tRTP = 2,
104 .tCKE = 3,
105 .tCKESR = 3,
106 .tFAW = 8
107};
108
109static const struct lpddr2_ac_timings const*
110 jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
111 &timings_jedec_200_mhz,
112 &timings_jedec_400_mhz
113};
114
115static const struct lpddr2_device_timings jedec_default_timings = {
116 .ac_timings = jedec_ac_timings,
117 .min_tck = &min_tck_jedec
118};
119
120void emif_get_device_timings(u32 emif_nr,
121 const struct lpddr2_device_timings **cs0_device_timings,
122 const struct lpddr2_device_timings **cs1_device_timings)
123{
124 /* Assume Identical devices on EMIF1 & EMIF2 */
125 *cs0_device_timings = &jedec_default_timings;
126 *cs1_device_timings = &jedec_default_timings;
127}
128#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */