blob: e88e6e2a9881d0dcd00af5477453afe219ed79b1 [file] [log] [blame]
Jason Liu23608e22011-11-25 00:18:02 +00001/*
2 * Based on the iomux-v3.c from Linux kernel:
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5 * <armlinux@phytec.de>
6 *
7 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Jason Liu23608e22011-11-25 00:18:02 +000010 */
11#include <common.h>
12#include <asm/io.h>
13#include <asm/arch/imx-regs.h>
Stefano Babic5d2ad2b2014-06-25 12:48:06 +020014#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
Tim Harvey5bf497e2014-06-02 16:13:24 -070015#include <asm/arch/sys_proto.h>
Stefano Babic67a04ab2014-06-06 10:58:47 +020016#endif
Troy Kiskyaf2a35f2012-07-19 08:18:22 +000017#include <asm/imx-common/iomux-v3.h>
Jason Liu23608e22011-11-25 00:18:02 +000018
19static void *base = (void *)IOMUXC_BASE_ADDR;
20
21/*
22 * configures a single pad in the iomuxer
23 */
Stefan Roese59efa052013-04-10 23:06:46 +000024void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
Jason Liu23608e22011-11-25 00:18:02 +000025{
26 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
27 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
28 u32 sel_input_ofs =
29 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
30 u32 sel_input =
31 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
32 u32 pad_ctrl_ofs =
33 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
34 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
35
Fabio Estevam98d2cff2014-04-29 10:15:46 -030036#if defined CONFIG_MX6SL
37 /* Check whether LVE bit needs to be set */
38 if (pad_ctrl & PAD_CTL_LVE) {
39 pad_ctrl &= ~PAD_CTL_LVE;
40 pad_ctrl |= PAD_CTL_LVE_BIT;
41 }
42#endif
43
Jason Liu23608e22011-11-25 00:18:02 +000044 if (mux_ctrl_ofs)
45 __raw_writel(mux_mode, base + mux_ctrl_ofs);
46
47 if (sel_input_ofs)
48 __raw_writel(sel_input, base + sel_input_ofs);
49
Alison Wangcfd701b2013-05-27 22:55:41 +000050#ifdef CONFIG_IOMUX_SHARE_CONF_REG
51 if (!(pad_ctrl & NO_PAD_CTRL))
52 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
53 base + pad_ctrl_ofs);
54#else
Jason Liu23608e22011-11-25 00:18:02 +000055 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
56 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
Alison Wangcfd701b2013-05-27 22:55:41 +000057#endif
Jason Liu23608e22011-11-25 00:18:02 +000058}
59
Tim Harvey5bf497e2014-06-02 16:13:24 -070060/* configures a list of pads within declared with IOMUX_PADS macro */
Stefan Roese59efa052013-04-10 23:06:46 +000061void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
62 unsigned count)
Jason Liu23608e22011-11-25 00:18:02 +000063{
Eric Nelson5ae28d22012-10-03 07:26:37 +000064 iomux_v3_cfg_t const *p = pad_list;
Tim Harvey5bf497e2014-06-02 16:13:24 -070065 int stride;
Jason Liu23608e22011-11-25 00:18:02 +000066 int i;
Jason Liu23608e22011-11-25 00:18:02 +000067
Tim Harvey5bf497e2014-06-02 16:13:24 -070068#if defined(CONFIG_MX6QDL)
69 stride = 2;
70 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
71 p += 1;
72#else
73 stride = 1;
74#endif
75 for (i = 0; i < count; i++) {
76 imx_iomux_v3_setup_pad(*p);
77 p += stride;
78 }
Jason Liu23608e22011-11-25 00:18:02 +000079}
Ye.Li8fe280f2014-10-30 18:53:49 +080080
81void imx_iomux_set_gpr_register(int group, int start_bit,
82 int num_bits, int value)
83{
84 int i = 0;
85 u32 reg;
86 reg = readl(base + group * 4);
87 while (num_bits) {
88 reg &= ~(1<<(start_bit + i));
89 i++;
90 num_bits--;
91 }
92 reg |= (value << start_bit);
93 writel(reg, base + group * 4);
94}