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gerrit.cesnet.cz / github / trini / u-boot / 7590d3cece3a4152bc60d6f1ca84b09f7abbf3cf / . / include / configs / pcm030.h
blob: 1c4d7227c7c93869f16adfc59160d5281225ba25 [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]1/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
34
35/*-----------------------------------------------------------------------------
36High Level Configuration Options
37(easy to change)
38-----------------------------------------------------------------------------*/
39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
42#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
43 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200[diff] [blame]44
45/*
46 * Valid values for CONFIG_SYS_TEXT_BASE are:
47 * 0xFFF00000 boot high (standard configuration)
48 * 0xFF000000 boot low
49 * 0x00100000 boot from RAM (for testing only)
50 */
51#ifndef CONFIG_SYS_TEXT_BASE
52#define CONFIG_SYS_TEXT_BASE 0xFFF00000
53#endif
54
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]55#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]56
57/*-----------------------------------------------------------------------------
58Serial console configuration
59-----------------------------------------------------------------------------*/
60#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
61 /*define gps port conf. */
62 /* register later on to */
63 /*enable UART function! */
64#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
65#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
66
67/*
68 * Command line configuration.
69 */
70#include <config_cmd_default.h>
71
72#define CONFIG_CMD_DATE
73#define CONFIG_CMD_DHCP
74#define CONFIG_CMD_EEPROM
75#define CONFIG_CMD_I2C
76#define CONFIG_CMD_JFFS2
77#define CONFIG_CMD_MII
78#define CONFIG_CMD_NFS
79#define CONFIG_CMD_PCI
80
81#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
82
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]83#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]84#define CONFIG_SYS_LOWBOOT 1
85#endif
86/* RAMBOOT will be defined automatically in memory section */
87
88#define CONFIG_JFFS2_CMDLINE
89#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
90#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
91 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
92
93/*-----------------------------------------------------------------------------
94Autobooting
95-----------------------------------------------------------------------------*/
96#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
97#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
98 /* even with bootdelay=0 */
99#undef CONFIG_BOOTARGS
100
101
102#define CONFIG_PREBOOT "echo;" \
103 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
104 "mount root filesystem over NFS;" \
105 "echo"
106
107#define CONFIG_EXTRA_ENV_SETTINGS \
108 "netdev=eth0\0" \
109 "uimage=uImage-pcm030\0" \
110 "oftree=oftree-pcm030.dtb\0" \
111 "jffs2=root-pcm030.jffs2\0" \
112 "uboot=u-boot-pcm030.bin\0" \
113 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
114 " $(mtdparts) rw\0" \
115 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
116 " rootfstype=jffs2\0" \
117 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
118 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
119 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
120 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
121 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
122 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
123 "0xfff40000\0" \
124 " cp.b 0x400000 0xff040000 $(filesize)\0" \
125 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
126 "cp.b 0x400000 0xff200000 $(filesize)\0" \
127 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
128 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
129 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
130 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
131 "unlock=yes\0" \
132 ""
133
134#define CONFIG_BOOTCOMMAND "run bcmd_flash"
135
136/*--------------------------------------------------------------------------
137IPB Bus clocking configuration.
138 ---------------------------------------------------------------------------*/
139#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
140
141/*-------------------------------------------------------------------------
142 * PCI Mapping:
143 * 0x40000000 - 0x4fffffff - PCI Memory
144 * 0x50000000 - 0x50ffffff - PCI IO Space
145 * -----------------------------------------------------------------------*/
146#define CONFIG_PCI 1
147#define CONFIG_PCI_PNP 1
148#define CONFIG_PCI_SCAN_SHOW 1
149#define CONFIG_PCI_MEM_BUS 0x40000000
150#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
151#define CONFIG_PCI_MEM_SIZE 0x10000000
152#define CONFIG_PCI_IO_BUS 0x50000000
153#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
154#define CONFIG_PCI_IO_SIZE 0x01000000
155#define CONFIG_SYS_XLB_PIPELINING 1
156
157/*---------------------------------------------------------------------------
158 I2C configuration
159---------------------------------------------------------------------------*/
160#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
161#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
162#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
163#define CONFIG_SYS_I2C_SLAVE 0x7F
164
165/*---------------------------------------------------------------------------
166 EEPROM CAT24WC32 configuration
167---------------------------------------------------------------------------*/
168#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
169#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
170#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
171#define CONFIG_SYS_EEPROM_SIZE 2048
172#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
173#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
174
175/*---------------------------------------------------------------------------
176RTC configuration
177---------------------------------------------------------------------------*/
178#define RTC
179#define CONFIG_RTC_PCF8563 1
180#define CONFIG_SYS_I2C_RTC_ADDR 0x51
181
182/*---------------------------------------------------------------------------
183 Flash configuration
184---------------------------------------------------------------------------*/
185
186#define CONFIG_SYS_FLASH_BASE 0xff000000
187#define CONFIG_SYS_FLASH_SIZE 0x01000000
188#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
189
190#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
191#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
192#define CONFIG_SYS_FLASH_EMPTY_INFO
193#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
194#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
195 /* (= chip selects) */
196#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
197
198/*
199 * Use also hardware protection. This seems required, as the BDI uses
200 * hardware protection. Without this, U-Boot can't work with this sectors,
201 * as its protection is software only by default
202 */
203#define CONFIG_SYS_FLASH_PROTECTION 1
204
205/*---------------------------------------------------------------------------
206 Environment settings
207---------------------------------------------------------------------------*/
208
209/* pcm030 ships with environment is EEPROM by default */
210#define CONFIG_ENV_IS_IN_EEPROM 1
211#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
212 /*beginning of the EEPROM */
213#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
214
215#define CONFIG_ENV_OVERWRITE 1
216
217/*-----------------------------------------------------------------------------
218 Memory map
219-----------------------------------------------------------------------------*/
220#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
221 /* bootloader or debugger config */
222#define CONFIG_SYS_SDRAM_BASE 0x00000000
223#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
224/* Use SRAM until RAM will be available */
225#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200[diff] [blame]226#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]227 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200[diff] [blame]228#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]229 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
231
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]233#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
234# define CONFIG_SYS_RAMBOOT 1
235#endif
236
237#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
238#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
239#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
240
241/*-----------------------------------------------------------------------------
242 Ethernet configuration
243-----------------------------------------------------------------------------*/
244#define CONFIG_MPC5xxx_FEC 1
245#define CONFIG_MPC5xxx_FEC_MII100
246#define CONFIG_PHY_ADDR 0x01
247
248/*---------------------------------------------------------------------------
249 GPIO configuration
250 ---------------------------------------------------------------------------*/
251
252/* GPIO port configuration
253 *
254 * Pin mapping:
255 *
256 * [29:31] = 01x
257 * PSC1_0 -> AC97 SDATA out
258 * PSC1_1 -> AC97 SDTA in
259 * PSC1_2 -> AC97 SYNC out
260 * PSC1_3 -> AC97 bitclock out
261 * PSC1_4 -> AC97 reset out
262 *
263 * [25:27] = 001
264 * PSC2_0 -> CAN 1 Tx out
265 * PSC2_1 -> CAN 1 Rx in
266 * PSC2_2 -> CAN 2 Tx out
267 * PSC2_3 -> CAN 2 Rx in
268 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
269 *
270 *
271 * [20:23] = 1100
272 * PSC3_0 -> UART Tx out
273 * PSC3_1 -> UART Rx in
274 * PSC3_2 -> UART RTS (in/out FIXME)
275 * PSC3_3 -> UART CTS (in/out FIXME)
276 * PSC3_4 -> LocalPlus Bus CS6 \
277 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
278 * PSC3_6 -> dedicated SPI MOSI out (master case)
279 * PSC3_7 -> dedicated SPI MISO in (master case)
280 * PSC3_8 -> dedicated SPI SS out (master case)
281 * PSC3_9 -> dedicated SPI CLK out (master case)
282 *
283 * [18:19] = 01
284 * USB_0 -> USB OE out
285 * USB_1 -> USB Tx- out
286 * USB_2 -> USB Tx+ out
287 * USB_3 -> USB RxD (in/out FIXME)
288 * USB_4 -> USB Rx+ in
289 * USB_5 -> USB Rx- in
290 * USB_6 -> USB PortPower out
291 * USB_7 -> USB speed out
292 * USB_8 -> USB suspend (in/out FIXME)
293 * USB_9 -> USB overcurrent in
294 *
295 * [17] = 0
296 * USB differential mode
297 *
298 * [16] = 0
299 * PCI enabled
300 *
301 * [12:15] = 0101
302 * ETH_0 -> ETH Txen
303 * ETH_1 -> ETH TxD0
304 * ETH_2 -> ETH TxD1
305 * ETH_3 -> ETH TxD2
306 * ETH_4 -> ETH TxD3
307 * ETH_5 -> ETH Txerr
308 * ETH_6 -> ETH MDC
309 * ETH_7 -> ETH MDIO
310 * ETH_8 -> ETH RxDv
311 * ETH_9 -> ETH RxCLK
312 * ETH_10 -> ETH Collision
313 * ETH_11 -> ETH TxD
314 * ETH_12 -> ETH RxD0
315 * ETH_13 -> ETH RxD1
316 * ETH_14 -> ETH RxD2
317 * ETH_15 -> ETH RxD3
318 * ETH_16 -> ETH Rxerr
319 * ETH_17 -> ETH CRS
320 *
321 * [9:11] = 101
322 * PSC6_0 -> UART RxD in
323 * PSC6_1 -> UART CTS (in/out FIXME)
324 * PSC6_2 -> UART TxD out
325 * PSC6_3 -> UART RTS (in/out FIXME)
326 *
327 * [2:3/6:7] = 00/11
328 * TMR_0 -> ATA_CS0 out
329 * TMR_1 -> ATA_CS1 out
330 * TMR_2 -> GPIO
331 * TMR_3 -> GPIO
332 * TMR_4 -> GPIO
333 * TMR_5 -> GPIO
334 * TMR_6 -> GPIO
335 * TMR_7 -> GPIO
336 * I2C_0 -> I2C 1 Clock out
337 * I2C_1 -> I2C 1 IO in/out
338 * I2C_2 -> I2C 2 Clock out
339 * I2C_3 -> I2C 2 IO in/out
340 *
341 * [4] = 1
342 * PSC3_5 is used as CS7
343 *
344 * [5] = 1
345 * PSC3_4 is used as CS6
346 *
347 * [1] = 0
348 * gpio_wkup_7 is GPIO
349 *
350 * [0] = 0
351 * gpio_wkup_6 is GPIO
352 *
353 */
354#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
355
356/*-----------------------------------------------------------------------------
357 Miscellaneous configurable options
358-------------------------------------------------------------------------------*/
359#define CONFIG_SYS_LONGHELP /* undef to save memory */
360#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
361
362#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
363
364#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
365#if defined(CONFIG_CMD_KGDB)
366#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
367#endif
368
369#if defined(CONFIG_CMD_KGDB)
370#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
371#else
372#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
373#endif
374#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
375 /* Print Buffer Size */
376#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
377#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
378
379#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
380#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
381
382#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
383#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
384
385#define CONFIG_DISPLAY_BOARDINFO 1
386
387/*-----------------------------------------------------------------------------
388 Various low-level settings
389-----------------------------------------------------------------------------*/
390#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
391#define CONFIG_SYS_HID0_FINAL HID0_ICE
392
393/* no burst access on the LPB */
394#define CONFIG_SYS_CS_BURST 0x00000000
395/* one deadcycle for the 33MHz statemachine */
396#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
397/* one additional waitstate for the 33MHz statemachine */
398#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
399#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
400#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
401
402#define CONFIG_SYS_RESET_ADDRESS 0xff000000
403
404/*-----------------------------------------------------------------------
405 * USB stuff
406 *-----------------------------------------------------------------------
407 */
408#define CONFIG_USB_CLOCK 0x0001BBBB
409#define CONFIG_USB_CONFIG 0x00001000
410
411/*---------------------------------------------------------------------------
412 IDE/ATA stuff Supports IDE harddisk
413----------------------------------------------------------------------------*/
414
415#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
416#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
417#undef CONFIG_IDE_LED /* LED for ide not supported */
418#define CONFIG_SYS_ATA_CS_ON_TIMER01
419#define CONFIG_IDE_RESET 1 /* reset for ide supported */
420#define CONFIG_IDE_PREINIT
421#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
422#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
423#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
424#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
425/* Offset for data I/O */
426#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
427/* Offset for normal register accesses */
428#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
429/* Offset for alternate registers */
430#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
431/* Interval between registers */
432#define CONFIG_SYS_ATA_STRIDE 4
433#define CONFIG_ATAPI 1
434
435/* we enable IDE and FAT support, so we also need partition support */
436#define CONFIG_DOS_PARTITION 1
437
438/* USB */
439#define CONFIG_USB_OHCI
440#define CONFIG_USB_STORAGE
441
442/* pass open firmware flat tree */
443#define CONFIG_OF_LIBFDT 1
444#define CONFIG_OF_BOARD_SETUP 1
445
446#define OF_CPU "PowerPC,5200@0"
447#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
448#define OF_SOC "soc5200@f0000000"
449#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
450
451#endif /* __CONFIG_H */