Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 1 | /* |
Kumar Gala | e5fe96b | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * mpc8569mds board configuration file |
| 25 | */ |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | /* High Level Configuration Options */ |
| 30 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 31 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 32 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ |
| 33 | #define CONFIG_MPC8569 1 /* MPC8569 specific */ |
| 34 | #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ |
| 35 | |
| 36 | #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ |
| 37 | |
Kumar Gala | e5fe96b | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 38 | #define CONFIG_SYS_SRIO |
| 39 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 40 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 41 | #define CONFIG_PCI 1 /* Disable PCI/PCIE */ |
| 42 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
| 43 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ |
| 44 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 45 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 46 | #define CONFIG_QE /* Enable QE */ |
| 47 | #define CONFIG_ENV_OVERWRITE |
| 48 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 49 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 50 | #ifndef __ASSEMBLY__ |
| 51 | extern unsigned long get_clock_freq(void); |
| 52 | #endif |
| 53 | /* Replace a call to get_clock_freq (after it is implemented)*/ |
Dave Liu | 6735104 | 2009-05-18 17:49:23 +0800 | [diff] [blame] | 54 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 55 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 56 | |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 57 | #ifdef CONFIG_ATM |
Liu Yu | c95d541 | 2009-11-27 15:31:52 +0800 | [diff] [blame] | 58 | #define CONFIG_PQ_MDS_PIB |
| 59 | #define CONFIG_PQ_MDS_PIB_ATM |
| 60 | #endif |
| 61 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 62 | /* |
| 63 | * These can be toggled for performance analysis, otherwise use default. |
| 64 | */ |
| 65 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 66 | #define CONFIG_BTB /* toggle branch predition */ |
| 67 | |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 68 | #ifdef CONFIG_NAND |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 69 | #define CONFIG_NAND_U_BOOT 1 |
| 70 | #define CONFIG_RAMBOOT_NAND 1 |
Haiying Wang | 96196a1 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 71 | #ifdef CONFIG_NAND_SPL |
| 72 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 |
| 73 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ |
| 74 | #else |
Kumar Gala | 00203c6 | 2011-01-31 15:57:01 -0600 | [diff] [blame] | 75 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
| 77 | #endif |
Haiying Wang | 96196a1 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 78 | #endif |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 79 | |
| 80 | #ifndef CONFIG_SYS_TEXT_BASE |
| 81 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 82 | #endif |
| 83 | |
Haiying Wang | 96196a1 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 84 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 85 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 86 | #endif |
| 87 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 88 | /* |
| 89 | * Only possible on E500 Version 2 or newer cores. |
| 90 | */ |
| 91 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 92 | |
| 93 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
Haiying Wang | 3aed550 | 2010-09-29 13:31:35 -0400 | [diff] [blame] | 94 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 95 | #define CONFIG_HWCONFIG |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 96 | |
| 97 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 98 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 99 | |
| 100 | /* |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 101 | * Config the L2 Cache as L2 SRAM |
| 102 | */ |
| 103 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 104 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 105 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 106 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 107 | |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 108 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 109 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 110 | |
Kumar Gala | 8d22ddc | 2011-11-09 09:10:49 -0600 | [diff] [blame] | 111 | #if defined(CONFIG_NAND_SPL) |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 112 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 113 | #endif |
| 114 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 115 | /* DDR Setup */ |
| 116 | #define CONFIG_FSL_DDR3 |
| 117 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 118 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 119 | #define CONFIG_DDR_SPD |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 120 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 121 | |
| 122 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 123 | |
| 124 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 125 | /* DDR is system memory*/ |
| 126 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 127 | |
| 128 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 129 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 130 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 131 | |
| 132 | /* I2C addresses of SPD EEPROMs */ |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 133 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 134 | |
| 135 | /* These are used when DDR doesn't use SPD. */ |
| 136 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ |
| 137 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| 138 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 139 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 140 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 |
| 141 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 |
| 142 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 |
| 143 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 |
| 144 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 |
| 145 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 |
| 146 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 |
| 147 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 |
| 148 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 149 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 |
| 150 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 151 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 152 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
| 153 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 |
| 154 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 |
| 155 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 |
| 156 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 157 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 158 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ |
| 159 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 |
| 160 | |
| 161 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 162 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 163 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
| 164 | |
| 165 | #undef CONFIG_CLOCKS_IN_MHZ |
| 166 | |
| 167 | /* |
| 168 | * Local Bus Definitions |
| 169 | */ |
| 170 | |
| 171 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
| 172 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 173 | |
| 174 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 |
| 175 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE |
| 176 | |
| 177 | /*Chip select 0 - Flash*/ |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 178 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
| 179 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 180 | |
Haiying Wang | 399b53c | 2009-05-20 12:30:32 -0400 | [diff] [blame] | 181 | /*Chip select 1 - BCSR*/ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 182 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
| 183 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 |
| 184 | |
Haiying Wang | 399b53c | 2009-05-20 12:30:32 -0400 | [diff] [blame] | 185 | /*Chip select 4 - PIB*/ |
| 186 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 |
| 187 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 |
| 188 | |
| 189 | /*Chip select 5 - PIB*/ |
| 190 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 |
| 191 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 |
| 192 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 193 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 194 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ |
| 195 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 196 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 197 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 198 | |
Kumar Gala | a55bb83 | 2010-11-29 14:32:11 -0600 | [diff] [blame] | 199 | #if defined(CONFIG_RAMBOOT_NAND) |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 200 | #define CONFIG_SYS_RAMBOOT |
Kumar Gala | a55bb83 | 2010-11-29 14:32:11 -0600 | [diff] [blame] | 201 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 202 | #else |
| 203 | #undef CONFIG_SYS_RAMBOOT |
| 204 | #endif |
| 205 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 206 | #define CONFIG_FLASH_CFI_DRIVER |
| 207 | #define CONFIG_SYS_FLASH_CFI |
| 208 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 209 | |
Anton Vorontsov | a29155e | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 210 | /* Chip select 3 - NAND */ |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 211 | #ifndef CONFIG_NAND_SPL |
Anton Vorontsov | a29155e | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 212 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 213 | #else |
| 214 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 |
| 215 | #endif |
| 216 | |
| 217 | /* NAND boot: 4K NAND loader config */ |
| 218 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
| 219 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) |
| 220 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| 221 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| 222 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| 223 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 224 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| 225 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| 226 | |
Anton Vorontsov | a29155e | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 227 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 228 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } |
| 229 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 230 | #define CONFIG_MTD_NAND_VERIFY_WRITE 1 |
| 231 | #define CONFIG_CMD_NAND 1 |
| 232 | #define CONFIG_NAND_FSL_ELBC 1 |
| 233 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
Matthew McClintock | a3055c5 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 234 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
Anton Vorontsov | a29155e | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 235 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 236 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 237 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 238 | | BR_V) /* valid */ |
Matthew McClintock | a3055c5 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 239 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Anton Vorontsov | a29155e | 2009-10-15 17:47:08 +0400 | [diff] [blame] | 240 | | OR_FCM_CSCT \ |
| 241 | | OR_FCM_CST \ |
| 242 | | OR_FCM_CHT \ |
| 243 | | OR_FCM_SCY_1 \ |
| 244 | | OR_FCM_TRLX \ |
| 245 | | OR_FCM_EHTR) |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 246 | |
| 247 | #ifdef CONFIG_RAMBOOT_NAND |
Matthew McClintock | a3055c5 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 248 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 249 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 250 | #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 251 | #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| 252 | #else |
| 253 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 254 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | a3055c5 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 255 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 256 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 257 | #endif |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 258 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 259 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
| 260 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ |
| 261 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 262 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
| 263 | |
| 264 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 265 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 266 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 267 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 268 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 269 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 270 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 271 | |
| 272 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
Haiying Wang | fb27949 | 2009-06-04 16:12:39 -0400 | [diff] [blame] | 273 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 274 | |
| 275 | /* Serial Port */ |
| 276 | #define CONFIG_CONS_INDEX 1 |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 277 | #define CONFIG_SERIAL_MULTI 1 |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 278 | #define CONFIG_SYS_NS16550 |
| 279 | #define CONFIG_SYS_NS16550_SERIAL |
| 280 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 281 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Kumar Gala | 9334190 | 2010-04-07 01:34:11 -0500 | [diff] [blame] | 282 | #ifdef CONFIG_NAND_SPL |
| 283 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 284 | #endif |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 285 | |
| 286 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 287 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 288 | |
| 289 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 290 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 291 | |
| 292 | /* Use the HUSH parser*/ |
| 293 | #define CONFIG_SYS_HUSH_PARSER |
| 294 | #ifdef CONFIG_SYS_HUSH_PARSER |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 295 | #endif |
| 296 | |
| 297 | /* pass open firmware flat tree */ |
| 298 | #define CONFIG_OF_LIBFDT 1 |
| 299 | #define CONFIG_OF_BOARD_SETUP 1 |
| 300 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 301 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 302 | /* |
| 303 | * I2C |
| 304 | */ |
| 305 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 306 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 307 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 308 | #define CONFIG_I2C_MULTI_BUS |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 309 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 310 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 311 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
| 312 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
| 313 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
| 314 | |
| 315 | /* |
| 316 | * I2C2 EEPROM |
| 317 | */ |
| 318 | #define CONFIG_ID_EEPROM |
| 319 | #ifdef CONFIG_ID_EEPROM |
| 320 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 321 | #endif |
| 322 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 323 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 324 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| 325 | |
| 326 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F |
| 327 | #define PLPPAR1_I2C2_VAL 0x00000000 |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 328 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 329 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
| 330 | #define PLPDIR1_I2C2_VAL 0x0000000F |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 331 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
Anton Vorontsov | c4ca10f | 2009-12-16 01:14:31 +0300 | [diff] [blame] | 332 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
| 333 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 |
| 334 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 |
| 335 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 336 | |
| 337 | /* |
| 338 | * General PCI |
| 339 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 |
| 340 | */ |
Kumar Gala | 94f2bc4 | 2010-12-17 10:18:07 -0600 | [diff] [blame] | 341 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 342 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
| 343 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
| 344 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
| 345 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 346 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
| 347 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 348 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
| 349 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ |
| 350 | |
Kumar Gala | e5fe96b | 2011-01-04 18:04:01 -0600 | [diff] [blame] | 351 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
| 352 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 |
| 353 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS |
| 354 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 355 | |
| 356 | #ifdef CONFIG_QE |
| 357 | /* |
| 358 | * QE UEC ethernet configuration |
| 359 | */ |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 360 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
| 361 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 362 | |
| 363 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) |
| 364 | #define CONFIG_UEC_ETH |
Kim Phillips | 78b7a8e | 2010-07-26 18:34:57 -0500 | [diff] [blame] | 365 | #define CONFIG_ETHPRIME "UEC0" |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 366 | #define CONFIG_PHY_MODE_NEED_CHANGE |
| 367 | |
| 368 | #define CONFIG_UEC_ETH1 /* GETH1 */ |
| 369 | #define CONFIG_HAS_ETH0 |
| 370 | |
| 371 | #ifdef CONFIG_UEC_ETH1 |
| 372 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
| 373 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 374 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 375 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
| 376 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH |
| 377 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 378 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 379 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 380 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 381 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ |
| 382 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
| 383 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 384 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 385 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 386 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 387 | #endif /* CONFIG_UEC_ETH1 */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 388 | |
| 389 | #define CONFIG_UEC_ETH2 /* GETH2 */ |
| 390 | #define CONFIG_HAS_ETH1 |
| 391 | |
| 392 | #ifdef CONFIG_UEC_ETH2 |
| 393 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
| 394 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 395 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 396 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
| 397 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH |
| 398 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 399 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 400 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 401 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 402 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ |
| 403 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH |
| 404 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 405 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 406 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 407 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 408 | #endif /* CONFIG_UEC_ETH2 */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 409 | |
Haiying Wang | 750098d | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 410 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
| 411 | #define CONFIG_HAS_ETH2 |
| 412 | |
| 413 | #ifdef CONFIG_UEC_ETH3 |
| 414 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ |
| 415 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 416 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | 750098d | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 417 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
| 418 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH |
| 419 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 420 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 421 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 422 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 423 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ |
| 424 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH |
| 425 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 426 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 427 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 428 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 429 | #endif /* CONFIG_UEC_ETH3 */ |
Haiying Wang | 750098d | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 430 | |
| 431 | #define CONFIG_UEC_ETH4 /* GETH4 */ |
| 432 | #define CONFIG_HAS_ETH3 |
| 433 | |
| 434 | #ifdef CONFIG_UEC_ETH4 |
| 435 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ |
| 436 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 437 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
Haiying Wang | 750098d | 2009-05-20 12:30:36 -0400 | [diff] [blame] | 438 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
| 439 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH |
| 440 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 441 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 442 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 443 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 444 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ |
| 445 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH |
| 446 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 447 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 448 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
Haiying Wang | f82107f | 2009-05-20 12:30:37 -0400 | [diff] [blame] | 449 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
| 450 | #endif /* CONFIG_UEC_ETH4 */ |
Haiying Wang | 3bd8e53 | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 451 | |
| 452 | #undef CONFIG_UEC_ETH6 /* GETH6 */ |
| 453 | #define CONFIG_HAS_ETH5 |
| 454 | |
| 455 | #ifdef CONFIG_UEC_ETH6 |
| 456 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ |
| 457 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE |
| 458 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE |
| 459 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH |
| 460 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 461 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 462 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
Haiying Wang | 3bd8e53 | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 463 | #endif /* CONFIG_UEC_ETH6 */ |
| 464 | |
| 465 | #undef CONFIG_UEC_ETH8 /* GETH8 */ |
| 466 | #define CONFIG_HAS_ETH7 |
| 467 | |
| 468 | #ifdef CONFIG_UEC_ETH8 |
| 469 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ |
| 470 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE |
| 471 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE |
| 472 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH |
| 473 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 |
Andy Fleming | 865ff85 | 2011-04-13 00:37:12 -0500 | [diff] [blame] | 474 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
Heiko Schocher | 582c55a | 2010-01-20 09:04:28 +0100 | [diff] [blame] | 475 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
Haiying Wang | 3bd8e53 | 2009-05-20 12:30:41 -0400 | [diff] [blame] | 476 | #endif /* CONFIG_UEC_ETH8 */ |
| 477 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 478 | #endif /* CONFIG_QE */ |
| 479 | |
| 480 | #if defined(CONFIG_PCI) |
| 481 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 482 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 483 | |
| 484 | #undef CONFIG_EEPRO100 |
| 485 | #undef CONFIG_TULIP |
Kumar Gala | 16855ec | 2010-11-09 23:19:50 -0600 | [diff] [blame] | 486 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 487 | |
| 488 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 489 | |
| 490 | #endif /* CONFIG_PCI */ |
| 491 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 492 | /* |
| 493 | * Environment |
| 494 | */ |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 495 | #if defined(CONFIG_SYS_RAMBOOT) |
| 496 | #if defined(CONFIG_RAMBOOT_NAND) |
| 497 | #define CONFIG_ENV_IS_IN_NAND 1 |
| 498 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 499 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) |
| 500 | #endif |
| 501 | #else |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 502 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Haiying Wang | fb27949 | 2009-06-04 16:12:39 -0400 | [diff] [blame] | 503 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
Haiying Wang | 1b8e4fa | 2010-09-29 13:44:14 -0400 | [diff] [blame] | 504 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 505 | #define CONFIG_ENV_SIZE 0x2000 |
Liu Yu | 674ef7b | 2010-01-18 19:03:28 +0800 | [diff] [blame] | 506 | #endif |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 507 | |
| 508 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 509 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 510 | |
| 511 | /* QE microcode/firmware address */ |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 512 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 513 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 514 | |
| 515 | /* |
| 516 | * BOOTP options |
| 517 | */ |
| 518 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 519 | #define CONFIG_BOOTP_BOOTPATH |
| 520 | #define CONFIG_BOOTP_GATEWAY |
| 521 | #define CONFIG_BOOTP_HOSTNAME |
| 522 | |
| 523 | |
| 524 | /* |
| 525 | * Command line configuration. |
| 526 | */ |
| 527 | #include <config_cmd_default.h> |
| 528 | |
| 529 | #define CONFIG_CMD_PING |
| 530 | #define CONFIG_CMD_I2C |
| 531 | #define CONFIG_CMD_MII |
| 532 | #define CONFIG_CMD_ELF |
| 533 | #define CONFIG_CMD_IRQ |
| 534 | #define CONFIG_CMD_SETEXPR |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 535 | #define CONFIG_CMD_REGINFO |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 536 | |
| 537 | #if defined(CONFIG_PCI) |
| 538 | #define CONFIG_CMD_PCI |
| 539 | #endif |
| 540 | |
| 541 | |
| 542 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 543 | |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 544 | #define CONFIG_MMC 1 |
| 545 | |
| 546 | #ifdef CONFIG_MMC |
| 547 | #define CONFIG_FSL_ESDHC |
Chenhui Zhao | a6da8b8 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 548 | #define CONFIG_FSL_ESDHC_PIN_MUX |
Anton Vorontsov | 7f52ed5 | 2009-10-15 17:47:06 +0400 | [diff] [blame] | 549 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 550 | #define CONFIG_CMD_MMC |
| 551 | #define CONFIG_GENERIC_MMC |
| 552 | #define CONFIG_CMD_EXT2 |
| 553 | #define CONFIG_CMD_FAT |
| 554 | #define CONFIG_DOS_PARTITION |
| 555 | #endif |
| 556 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 557 | /* |
| 558 | * Miscellaneous configurable options |
| 559 | */ |
Kim Phillips | 5be58f5 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 560 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 561 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 562 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 563 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 564 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 565 | #if defined(CONFIG_CMD_KGDB) |
| 566 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ |
| 567 | #else |
| 568 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 569 | #endif |
| 570 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 571 | /* Print Buffer Size */ |
| 572 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
| 573 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 574 | /* Boot Argument Buffer Size */ |
| 575 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 576 | |
| 577 | /* |
| 578 | * For booting Linux, the board info and command line data |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 579 | * have to be in the first 64 MB of memory, since this is |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 580 | * the maximum mapped by the Linux kernel during initialization. |
| 581 | */ |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 582 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 583 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 584 | |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 585 | #if defined(CONFIG_CMD_KGDB) |
| 586 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 587 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 588 | #endif |
| 589 | |
| 590 | /* |
| 591 | * Environment Configuration |
| 592 | */ |
| 593 | #define CONFIG_HOSTNAME mpc8569mds |
Joe Hershberger | 8b3637c | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 594 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | b3f44c2 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 595 | #define CONFIG_BOOTFILE "your.uImage" |
Haiying Wang | 765547d | 2009-03-27 17:02:45 -0400 | [diff] [blame] | 596 | |
| 597 | #define CONFIG_SERVERIP 192.168.1.1 |
| 598 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 599 | #define CONFIG_NETMASK 255.255.255.0 |
| 600 | |
| 601 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
| 602 | |
| 603 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 604 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 605 | |
| 606 | #define CONFIG_BAUDRATE 115200 |
| 607 | |
| 608 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 609 | "netdev=eth0\0" \ |
| 610 | "consoledev=ttyS0\0" \ |
| 611 | "ramdiskaddr=600000\0" \ |
| 612 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 613 | "fdtaddr=400000\0" \ |
| 614 | "fdtfile=your.fdt.dtb\0" \ |
| 615 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 616 | "nfsroot=$serverip:$rootpath " \ |
| 617 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 618 | "console=$consoledev,$baudrate $othbootargs\0" \ |
| 619 | "ramargs=setenv bootargs root=/dev/ram rw " \ |
| 620 | "console=$consoledev,$baudrate $othbootargs\0" \ |
| 621 | |
| 622 | #define CONFIG_NFSBOOTCOMMAND \ |
| 623 | "run nfsargs;" \ |
| 624 | "tftp $loadaddr $bootfile;" \ |
| 625 | "tftp $fdtaddr $fdtfile;" \ |
| 626 | "bootm $loadaddr - $fdtaddr" |
| 627 | |
| 628 | #define CONFIG_RAMBOOTCOMMAND \ |
| 629 | "run ramargs;" \ |
| 630 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 631 | "tftp $loadaddr $bootfile;" \ |
| 632 | "bootm $loadaddr $ramdiskaddr" |
| 633 | |
| 634 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 635 | |
| 636 | #endif /* __CONFIG_H */ |