blob: 129777c71755a327a8da460069481aa2ac194580 [file] [log] [blame]
wdenk2262cfe2002-11-18 00:14:45 +00001/*
Graeme Russdbf71152011-04-13 19:43:26 +10002 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
wdenk2262cfe2002-11-18 00:14:45 +00005 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk8bde7f72003-06-27 21:31:46 +00007 *
wdenk2262cfe2002-11-18 00:14:45 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * (C) Copyright 2002
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
15 *
Bin Meng52f952b2014-11-09 22:18:56 +080016 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
18 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020019 * SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +000020 */
21
wdenk2262cfe2002-11-18 00:14:45 +000022#include <common.h>
23#include <command.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080024#include <dm.h>
Simon Glass200182a2014-10-10 08:21:55 -060025#include <errno.h>
26#include <malloc.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +000027#include <asm/control_regs.h>
Simon Glass200182a2014-10-10 08:21:55 -060028#include <asm/cpu.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080029#include <asm/lapic.h>
30#include <asm/mp.h>
Bin Meng43dd22f2015-07-06 16:31:30 +080031#include <asm/msr.h>
32#include <asm/mtrr.h>
Simon Glassa49e3c72014-11-12 22:42:26 -070033#include <asm/post.h>
Graeme Russc53fd2b2011-02-12 15:11:30 +110034#include <asm/processor.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110035#include <asm/processor-flags.h>
Graeme Russ3f5f18d2008-12-07 10:29:02 +110036#include <asm/interrupt.h>
Bin Meng5e2400e2015-04-24 18:10:04 +080037#include <asm/tables.h>
Gabe Black60a9b6b2011-11-16 23:32:50 +000038#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000039
Bin Meng52f952b2014-11-09 22:18:56 +080040DECLARE_GLOBAL_DATA_PTR;
41
Graeme Russdbf71152011-04-13 19:43:26 +100042/*
43 * Constructor for a conventional segment GDT (or LDT) entry
44 * This is a macro so it can be used in initialisers
45 */
Graeme Russ59c6d0e2010-10-07 20:03:21 +110046#define GDT_ENTRY(flags, base, limit) \
47 ((((base) & 0xff000000ULL) << (56-24)) | \
48 (((flags) & 0x0000f0ffULL) << 40) | \
49 (((limit) & 0x000f0000ULL) << (48-16)) | \
50 (((base) & 0x00ffffffULL) << 16) | \
51 (((limit) & 0x0000ffffULL)))
52
Graeme Russ59c6d0e2010-10-07 20:03:21 +110053struct gdt_ptr {
54 u16 len;
55 u32 ptr;
Graeme Russ717979f2011-11-08 02:33:13 +000056} __packed;
Graeme Russ59c6d0e2010-10-07 20:03:21 +110057
Bin Meng52f952b2014-11-09 22:18:56 +080058struct cpu_device_id {
59 unsigned vendor;
60 unsigned device;
61};
62
63struct cpuinfo_x86 {
64 uint8_t x86; /* CPU family */
65 uint8_t x86_vendor; /* CPU vendor */
66 uint8_t x86_model;
67 uint8_t x86_mask;
68};
69
70/*
71 * List of cpu vendor strings along with their normalized
72 * id values.
73 */
74static struct {
75 int vendor;
76 const char *name;
77} x86_vendors[] = {
78 { X86_VENDOR_INTEL, "GenuineIntel", },
79 { X86_VENDOR_CYRIX, "CyrixInstead", },
80 { X86_VENDOR_AMD, "AuthenticAMD", },
81 { X86_VENDOR_UMC, "UMC UMC UMC ", },
82 { X86_VENDOR_NEXGEN, "NexGenDriven", },
83 { X86_VENDOR_CENTAUR, "CentaurHauls", },
84 { X86_VENDOR_RISE, "RiseRiseRise", },
85 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
86 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
87 { X86_VENDOR_NSC, "Geode by NSC", },
88 { X86_VENDOR_SIS, "SiS SiS SiS ", },
89};
90
91static const char *const x86_vendor_name[] = {
92 [X86_VENDOR_INTEL] = "Intel",
93 [X86_VENDOR_CYRIX] = "Cyrix",
94 [X86_VENDOR_AMD] = "AMD",
95 [X86_VENDOR_UMC] = "UMC",
96 [X86_VENDOR_NEXGEN] = "NexGen",
97 [X86_VENDOR_CENTAUR] = "Centaur",
98 [X86_VENDOR_RISE] = "Rise",
99 [X86_VENDOR_TRANSMETA] = "Transmeta",
100 [X86_VENDOR_NSC] = "NSC",
101 [X86_VENDOR_SIS] = "SiS",
102};
103
Graeme Russ74bfbe12011-12-29 21:45:33 +1100104static void load_ds(u32 segment)
Graeme Russ59c6d0e2010-10-07 20:03:21 +1100105{
Graeme Russ74bfbe12011-12-29 21:45:33 +1100106 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
107}
Graeme Russ59c6d0e2010-10-07 20:03:21 +1100108
Graeme Russ74bfbe12011-12-29 21:45:33 +1100109static void load_es(u32 segment)
110{
111 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
112}
Graeme Russ59c6d0e2010-10-07 20:03:21 +1100113
Graeme Russ74bfbe12011-12-29 21:45:33 +1100114static void load_fs(u32 segment)
115{
116 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
117}
118
119static void load_gs(u32 segment)
120{
121 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
122}
123
124static void load_ss(u32 segment)
125{
126 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
127}
128
129static void load_gdt(const u64 *boot_gdt, u16 num_entries)
130{
131 struct gdt_ptr gdt;
132
Simon Glasse34aef12014-11-14 20:56:29 -0700133 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
Graeme Russ74bfbe12011-12-29 21:45:33 +1100134 gdt.ptr = (u32)boot_gdt;
135
136 asm volatile("lgdtl %0\n" : : "m" (gdt));
Graeme Russ59c6d0e2010-10-07 20:03:21 +1100137}
138
Graeme Russ9e6c5722011-12-31 22:58:15 +1100139void setup_gdt(gd_t *id, u64 *gdt_addr)
140{
Simon Glass52845292015-04-28 20:25:15 -0600141 id->arch.gdt = gdt_addr;
Graeme Russ9e6c5722011-12-31 22:58:15 +1100142 /* CS: code, read/execute, 4 GB, base 0 */
143 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
144
145 /* DS: data, read/write, 4 GB, base 0 */
146 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
147
148 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
Simon Glass5a35e6c2012-12-13 20:48:41 +0000149 id->arch.gd_addr = id;
Simon Glass0cecc3b2012-12-13 20:48:42 +0000150 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
Simon Glass5a35e6c2012-12-13 20:48:41 +0000151 (ulong)&id->arch.gd_addr, 0xfffff);
Graeme Russ9e6c5722011-12-31 22:58:15 +1100152
153 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
Simon Glasse34aef12014-11-14 20:56:29 -0700154 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
Graeme Russ9e6c5722011-12-31 22:58:15 +1100155
156 /* 16-bit DS: data, read/write, 64 kB, base 0 */
Simon Glasse34aef12014-11-14 20:56:29 -0700157 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
158
159 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
160 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
Graeme Russ9e6c5722011-12-31 22:58:15 +1100161
162 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
163 load_ds(X86_GDT_ENTRY_32BIT_DS);
164 load_es(X86_GDT_ENTRY_32BIT_DS);
165 load_gs(X86_GDT_ENTRY_32BIT_DS);
166 load_ss(X86_GDT_ENTRY_32BIT_DS);
167 load_fs(X86_GDT_ENTRY_32BIT_FS);
168}
169
Bin Meng002610f2015-06-07 11:33:13 +0800170#ifdef CONFIG_HAVE_FSP
171/*
172 * Setup FSP execution environment GDT
173 *
174 * Per Intel FSP external architecture specification, before calling any FSP
175 * APIs, we need make sure the system is in flat 32-bit mode and both the code
176 * and data selectors should have full 4GB access range. Here we reuse the one
177 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
178 */
179void setup_fsp_gdt(void)
180{
181 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
182 load_ds(X86_GDT_ENTRY_32BIT_DS);
183 load_ss(X86_GDT_ENTRY_32BIT_DS);
184 load_es(X86_GDT_ENTRY_32BIT_DS);
185 load_fs(X86_GDT_ENTRY_32BIT_DS);
186 load_gs(X86_GDT_ENTRY_32BIT_DS);
187}
188#endif
189
Gabe Blackf30fc4d2012-10-20 12:33:10 +0000190int __weak x86_cleanup_before_linux(void)
191{
Simon Glass79497032013-04-17 16:13:35 +0000192#ifdef CONFIG_BOOTSTAGE_STASH
Simon Glassee2b2432015-03-02 17:04:37 -0700193 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
Simon Glass79497032013-04-17 16:13:35 +0000194 CONFIG_BOOTSTAGE_STASH_SIZE);
195#endif
196
Gabe Blackf30fc4d2012-10-20 12:33:10 +0000197 return 0;
198}
199
Bin Meng52f952b2014-11-09 22:18:56 +0800200/*
201 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
202 * by the fact that they preserve the flags across the division of 5/2.
203 * PII and PPro exhibit this behavior too, but they have cpuid available.
204 */
205
206/*
207 * Perform the Cyrix 5/2 test. A Cyrix won't change
208 * the flags, while other 486 chips will.
209 */
210static inline int test_cyrix_52div(void)
211{
212 unsigned int test;
213
214 __asm__ __volatile__(
215 "sahf\n\t" /* clear flags (%eax = 0x0005) */
216 "div %b2\n\t" /* divide 5 by 2 */
217 "lahf" /* store flags into %ah */
218 : "=a" (test)
219 : "0" (5), "q" (2)
220 : "cc");
221
222 /* AH is 0x02 on Cyrix after the divide.. */
223 return (unsigned char) (test >> 8) == 0x02;
224}
225
226/*
227 * Detect a NexGen CPU running without BIOS hypercode new enough
228 * to have CPUID. (Thanks to Herbert Oppmann)
229 */
230
231static int deep_magic_nexgen_probe(void)
232{
233 int ret;
234
235 __asm__ __volatile__ (
236 " movw $0x5555, %%ax\n"
237 " xorw %%dx,%%dx\n"
238 " movw $2, %%cx\n"
239 " divw %%cx\n"
240 " movl $0, %%eax\n"
241 " jnz 1f\n"
242 " movl $1, %%eax\n"
243 "1:\n"
244 : "=a" (ret) : : "cx", "dx");
245 return ret;
246}
247
248static bool has_cpuid(void)
249{
250 return flag_is_changeable_p(X86_EFLAGS_ID);
251}
252
Bin Meng49491662015-01-22 11:29:40 +0800253static bool has_mtrr(void)
254{
255 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
256}
257
Bin Meng52f952b2014-11-09 22:18:56 +0800258static int build_vendor_name(char *vendor_name)
259{
260 struct cpuid_result result;
261 result = cpuid(0x00000000);
262 unsigned int *name_as_ints = (unsigned int *)vendor_name;
263
264 name_as_ints[0] = result.ebx;
265 name_as_ints[1] = result.edx;
266 name_as_ints[2] = result.ecx;
267
268 return result.eax;
269}
270
271static void identify_cpu(struct cpu_device_id *cpu)
272{
273 char vendor_name[16];
274 int i;
275
276 vendor_name[0] = '\0'; /* Unset */
Simon Glass6cba6b92014-11-12 20:27:55 -0700277 cpu->device = 0; /* fix gcc 4.4.4 warning */
Bin Meng52f952b2014-11-09 22:18:56 +0800278
279 /* Find the id and vendor_name */
280 if (!has_cpuid()) {
281 /* Its a 486 if we can modify the AC flag */
282 if (flag_is_changeable_p(X86_EFLAGS_AC))
283 cpu->device = 0x00000400; /* 486 */
284 else
285 cpu->device = 0x00000300; /* 386 */
286 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
287 memcpy(vendor_name, "CyrixInstead", 13);
288 /* If we ever care we can enable cpuid here */
289 }
290 /* Detect NexGen with old hypercode */
291 else if (deep_magic_nexgen_probe())
292 memcpy(vendor_name, "NexGenDriven", 13);
293 }
294 if (has_cpuid()) {
295 int cpuid_level;
296
297 cpuid_level = build_vendor_name(vendor_name);
298 vendor_name[12] = '\0';
299
300 /* Intel-defined flags: level 0x00000001 */
301 if (cpuid_level >= 0x00000001) {
302 cpu->device = cpuid_eax(0x00000001);
303 } else {
304 /* Have CPUID level 0 only unheard of */
305 cpu->device = 0x00000400;
306 }
307 }
308 cpu->vendor = X86_VENDOR_UNKNOWN;
309 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
310 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
311 cpu->vendor = x86_vendors[i].vendor;
312 break;
313 }
314 }
315}
316
317static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
318{
319 c->x86 = (tfms >> 8) & 0xf;
320 c->x86_model = (tfms >> 4) & 0xf;
321 c->x86_mask = tfms & 0xf;
322 if (c->x86 == 0xf)
323 c->x86 += (tfms >> 20) & 0xff;
324 if (c->x86 >= 0x6)
325 c->x86_model += ((tfms >> 16) & 0xF) << 4;
326}
327
Graeme Russ0ea76e92011-02-12 15:11:35 +1100328int x86_cpu_init_f(void)
wdenk2262cfe2002-11-18 00:14:45 +0000329{
Graeme Russ0c24c9c2011-02-12 15:11:32 +1100330 const u32 em_rst = ~X86_CR0_EM;
331 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
332
Simon Glasse49ccea2015-08-04 12:34:00 -0600333 if (ll_boot_init()) {
334 /* initialize FPU, reset EM, set MP and NE */
335 asm ("fninit\n" \
336 "movl %%cr0, %%eax\n" \
337 "andl %0, %%eax\n" \
338 "orl %1, %%eax\n" \
339 "movl %%eax, %%cr0\n" \
340 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
341 }
wdenk8bde7f72003-06-27 21:31:46 +0000342
Bin Meng52f952b2014-11-09 22:18:56 +0800343 /* identify CPU via cpuid and store the decoded info into gd->arch */
344 if (has_cpuid()) {
345 struct cpu_device_id cpu;
346 struct cpuinfo_x86 c;
347
348 identify_cpu(&cpu);
349 get_fms(&c, cpu.device);
350 gd->arch.x86 = c.x86;
351 gd->arch.x86_vendor = cpu.vendor;
352 gd->arch.x86_model = c.x86_model;
353 gd->arch.x86_mask = c.x86_mask;
354 gd->arch.x86_device = cpu.device;
Bin Meng49491662015-01-22 11:29:40 +0800355
356 gd->arch.has_mtrr = has_mtrr();
Bin Meng52f952b2014-11-09 22:18:56 +0800357 }
Simon Glassb9da5082015-07-03 18:28:27 -0600358 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
359 gd->pci_ram_top = 0x80000000U;
Bin Meng52f952b2014-11-09 22:18:56 +0800360
Bin Meng43dd22f2015-07-06 16:31:30 +0800361 /* Configure fixed range MTRRs for some legacy regions */
362 if (gd->arch.has_mtrr) {
363 u64 mtrr_cap;
364
365 mtrr_cap = native_read_msr(MTRR_CAP_MSR);
366 if (mtrr_cap & MTRR_CAP_FIX) {
367 /* Mark the VGA RAM area as uncacheable */
Bin Meng8ba25ee2015-07-15 16:23:38 +0800368 native_write_msr(MTRR_FIX_16K_A0000_MSR,
369 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
370 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
Bin Meng43dd22f2015-07-06 16:31:30 +0800371
Bin Meng8ba25ee2015-07-15 16:23:38 +0800372 /*
373 * Mark the PCI ROM area as cacheable to improve ROM
374 * execution performance.
375 */
376 native_write_msr(MTRR_FIX_4K_C0000_MSR,
377 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
378 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
379 native_write_msr(MTRR_FIX_4K_C8000_MSR,
380 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
381 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
382 native_write_msr(MTRR_FIX_4K_D0000_MSR,
383 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
384 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
385 native_write_msr(MTRR_FIX_4K_D8000_MSR,
386 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
387 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
Bin Meng43dd22f2015-07-06 16:31:30 +0800388
389 /* Enable the fixed range MTRRs */
390 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
391 }
392 }
393
Graeme Russ1c409bc2009-11-24 20:04:21 +1100394 return 0;
395}
396
Graeme Russd6532442011-12-27 22:46:43 +1100397void x86_enable_caches(void)
398{
Stefan Reinauer095593c2012-12-02 04:49:50 +0000399 unsigned long cr0;
Graeme Russ0ea76e92011-02-12 15:11:35 +1100400
Stefan Reinauer095593c2012-12-02 04:49:50 +0000401 cr0 = read_cr0();
402 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
403 write_cr0(cr0);
404 wbinvd();
Graeme Russd6532442011-12-27 22:46:43 +1100405}
406void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
Graeme Russ0ea76e92011-02-12 15:11:35 +1100407
Stefan Reinauer095593c2012-12-02 04:49:50 +0000408void x86_disable_caches(void)
409{
410 unsigned long cr0;
411
412 cr0 = read_cr0();
413 cr0 |= X86_CR0_NW | X86_CR0_CD;
414 wbinvd();
415 write_cr0(cr0);
416 wbinvd();
417}
418void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
419
Graeme Russd6532442011-12-27 22:46:43 +1100420int x86_init_cache(void)
421{
422 enable_caches();
423
wdenk2262cfe2002-11-18 00:14:45 +0000424 return 0;
425}
Graeme Russd6532442011-12-27 22:46:43 +1100426int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk2262cfe2002-11-18 00:14:45 +0000427
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200428int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk2262cfe2002-11-18 00:14:45 +0000429{
Graeme Russ717979f2011-11-08 02:33:13 +0000430 printf("resetting ...\n");
Graeme Russdbf71152011-04-13 19:43:26 +1000431
432 /* wait 50 ms */
433 udelay(50000);
wdenk2262cfe2002-11-18 00:14:45 +0000434 disable_interrupts();
435 reset_cpu(0);
436
437 /*NOTREACHED*/
438 return 0;
439}
440
Graeme Russ717979f2011-11-08 02:33:13 +0000441void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk2262cfe2002-11-18 00:14:45 +0000442{
443 asm("wbinvd\n");
wdenk2262cfe2002-11-18 00:14:45 +0000444}
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100445
Simon Glasse1ffd812014-11-06 13:20:08 -0700446__weak void reset_cpu(ulong addr)
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100447{
Simon Glassff6a8f32015-04-28 20:11:29 -0600448 /* Do a hard reset through the chipset's reset control register */
449 outb(SYS_RST | RST_CPU, PORT_RESET);
450 for (;;)
451 cpu_hlt();
452}
453
454void x86_full_reset(void)
455{
456 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100457}
Stefan Reinauer095593c2012-12-02 04:49:50 +0000458
459int dcache_status(void)
460{
Simon Glassb6c9a202015-07-31 09:31:26 -0600461 return !(read_cr0() & X86_CR0_CD);
Stefan Reinauer095593c2012-12-02 04:49:50 +0000462}
463
464/* Define these functions to allow ehch-hcd to function */
465void flush_dcache_range(unsigned long start, unsigned long stop)
466{
467}
468
469void invalidate_dcache_range(unsigned long start, unsigned long stop)
470{
471}
Simon Glass89371402013-02-28 19:26:11 +0000472
473void dcache_enable(void)
474{
475 enable_caches();
476}
477
478void dcache_disable(void)
479{
480 disable_caches();
481}
482
483void icache_enable(void)
484{
485}
486
487void icache_disable(void)
488{
489}
490
491int icache_status(void)
492{
493 return 1;
494}
Simon Glass7bddac92014-10-10 08:21:52 -0600495
496void cpu_enable_paging_pae(ulong cr3)
497{
498 __asm__ __volatile__(
499 /* Load the page table address */
500 "movl %0, %%cr3\n"
501 /* Enable pae */
502 "movl %%cr4, %%eax\n"
503 "orl $0x00000020, %%eax\n"
504 "movl %%eax, %%cr4\n"
505 /* Enable paging */
506 "movl %%cr0, %%eax\n"
507 "orl $0x80000000, %%eax\n"
508 "movl %%eax, %%cr0\n"
509 :
510 : "r" (cr3)
511 : "eax");
512}
513
514void cpu_disable_paging_pae(void)
515{
516 /* Turn off paging */
517 __asm__ __volatile__ (
518 /* Disable paging */
519 "movl %%cr0, %%eax\n"
520 "andl $0x7fffffff, %%eax\n"
521 "movl %%eax, %%cr0\n"
522 /* Disable pae */
523 "movl %%cr4, %%eax\n"
524 "andl $0xffffffdf, %%eax\n"
525 "movl %%eax, %%cr4\n"
526 :
527 :
528 : "eax");
529}
Simon Glass92cc94a2014-10-10 08:21:54 -0600530
Simon Glass92cc94a2014-10-10 08:21:54 -0600531static bool can_detect_long_mode(void)
532{
Bin Meng52f952b2014-11-09 22:18:56 +0800533 return cpuid_eax(0x80000000) > 0x80000000UL;
Simon Glass92cc94a2014-10-10 08:21:54 -0600534}
535
536static bool has_long_mode(void)
537{
Bin Meng52f952b2014-11-09 22:18:56 +0800538 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
Simon Glass92cc94a2014-10-10 08:21:54 -0600539}
540
541int cpu_has_64bit(void)
542{
543 return has_cpuid() && can_detect_long_mode() &&
544 has_long_mode();
545}
546
Bin Meng52f952b2014-11-09 22:18:56 +0800547const char *cpu_vendor_name(int vendor)
548{
549 const char *name;
550 name = "<invalid cpu vendor>";
551 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
552 (x86_vendor_name[vendor] != 0))
553 name = x86_vendor_name[vendor];
554
555 return name;
556}
557
Simon Glass727c1a92014-11-10 18:00:26 -0700558char *cpu_get_name(char *name)
Bin Meng52f952b2014-11-09 22:18:56 +0800559{
Simon Glass727c1a92014-11-10 18:00:26 -0700560 unsigned int *name_as_ints = (unsigned int *)name;
Bin Meng52f952b2014-11-09 22:18:56 +0800561 struct cpuid_result regs;
Simon Glass727c1a92014-11-10 18:00:26 -0700562 char *ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800563 int i;
564
Simon Glass727c1a92014-11-10 18:00:26 -0700565 /* This bit adds up to 48 bytes */
Bin Meng52f952b2014-11-09 22:18:56 +0800566 for (i = 0; i < 3; i++) {
567 regs = cpuid(0x80000002 + i);
568 name_as_ints[i * 4 + 0] = regs.eax;
569 name_as_ints[i * 4 + 1] = regs.ebx;
570 name_as_ints[i * 4 + 2] = regs.ecx;
571 name_as_ints[i * 4 + 3] = regs.edx;
572 }
Simon Glass727c1a92014-11-10 18:00:26 -0700573 name[CPU_MAX_NAME_LEN - 1] = '\0';
Bin Meng52f952b2014-11-09 22:18:56 +0800574
575 /* Skip leading spaces. */
Simon Glass727c1a92014-11-10 18:00:26 -0700576 ptr = name;
577 while (*ptr == ' ')
578 ptr++;
Bin Meng52f952b2014-11-09 22:18:56 +0800579
Simon Glass727c1a92014-11-10 18:00:26 -0700580 return ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800581}
582
Simon Glass727c1a92014-11-10 18:00:26 -0700583int default_print_cpuinfo(void)
Simon Glass92cc94a2014-10-10 08:21:54 -0600584{
Bin Meng52f952b2014-11-09 22:18:56 +0800585 printf("CPU: %s, vendor %s, device %xh\n",
586 cpu_has_64bit() ? "x86_64" : "x86",
587 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
Simon Glass92cc94a2014-10-10 08:21:54 -0600588
589 return 0;
590}
Simon Glass200182a2014-10-10 08:21:55 -0600591
592#define PAGETABLE_SIZE (6 * 4096)
593
594/**
595 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
596 *
597 * @pgtable: Pointer to a 24iKB block of memory
598 */
599static void build_pagetable(uint32_t *pgtable)
600{
601 uint i;
602
603 memset(pgtable, '\0', PAGETABLE_SIZE);
604
605 /* Level 4 needs a single entry */
606 pgtable[0] = (uint32_t)&pgtable[1024] + 7;
607
608 /* Level 3 has one 64-bit entry for each GiB of memory */
609 for (i = 0; i < 4; i++) {
610 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
611 0x1000 * i + 7;
612 }
613
614 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
615 for (i = 0; i < 2048; i++)
616 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
617}
618
619int cpu_jump_to_64bit(ulong setup_base, ulong target)
620{
621 uint32_t *pgtable;
622
623 pgtable = memalign(4096, PAGETABLE_SIZE);
624 if (!pgtable)
625 return -ENOMEM;
626
627 build_pagetable(pgtable);
628 cpu_call64((ulong)pgtable, setup_base, target);
629 free(pgtable);
630
631 return -EFAULT;
632}
Simon Glassa49e3c72014-11-12 22:42:26 -0700633
634void show_boot_progress(int val)
635{
636#if MIN_PORT80_KCLOCKS_DELAY
637 /*
638 * Scale the time counter reading to avoid using 64 bit arithmetics.
639 * Can't use get_timer() here becuase it could be not yet
640 * initialized or even implemented.
641 */
642 if (!gd->arch.tsc_prev) {
643 gd->arch.tsc_base_kclocks = rdtsc() / 1000;
644 gd->arch.tsc_prev = 0;
645 } else {
646 uint32_t now;
647
648 do {
649 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
650 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
651 gd->arch.tsc_prev = now;
652 }
653#endif
654 outb(val, POST_PORT);
655}
Bin Meng5e2400e2015-04-24 18:10:04 +0800656
657#ifndef CONFIG_SYS_COREBOOT
658int last_stage_init(void)
659{
660 write_tables();
661
662 return 0;
663}
664#endif
Simon Glassbcb0c612015-04-29 22:26:01 -0600665
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800666#ifdef CONFIG_SMP
667static int enable_smis(struct udevice *cpu, void *unused)
668{
669 return 0;
670}
671
672static struct mp_flight_record mp_steps[] = {
673 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
674 /* Wait for APs to finish initialization before proceeding */
675 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
676};
677
678static int x86_mp_init(void)
679{
680 struct mp_params mp_params;
681
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800682 mp_params.parallel_microcode_load = 0,
683 mp_params.flight_plan = &mp_steps[0];
684 mp_params.num_records = ARRAY_SIZE(mp_steps);
685 mp_params.microcode_pointer = 0;
686
687 if (mp_init(&mp_params)) {
688 printf("Warning: MP init failure\n");
689 return -EIO;
690 }
691
692 return 0;
693}
694#endif
695
Simon Glassbcb0c612015-04-29 22:26:01 -0600696__weak int x86_init_cpus(void)
697{
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800698#ifdef CONFIG_SMP
699 debug("Init additional CPUs\n");
700 x86_mp_init();
Bin Mengc77b8912015-07-22 01:21:12 -0700701#else
702 struct udevice *dev;
703
704 /*
705 * This causes the cpu-x86 driver to be probed.
706 * We don't check return value here as we want to allow boards
707 * which have not been converted to use cpu uclass driver to boot.
708 */
709 uclass_first_device(UCLASS_CPU, &dev);
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800710#endif
711
Simon Glassbcb0c612015-04-29 22:26:01 -0600712 return 0;
713}
714
715int cpu_init_r(void)
716{
Simon Glasse49ccea2015-08-04 12:34:00 -0600717 if (ll_boot_init())
718 return x86_init_cpus();
719
720 return 0;
Simon Glassbcb0c612015-04-29 22:26:01 -0600721}