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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/* U-Boot - Startup Code for PowerPC based Embedded Boards
26 *
27 *
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
30 * in memory, but as long we don't jump around before relocating.
31 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
35 * the flash somewhere up there in the memorymap.
36 *
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
39 */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020040#include <asm-offsets.h>
wdenkc6097192002-11-03 00:24:07 +000041#include <config.h>
42#include <mpc824x.h>
Peter Tyser561858e2008-11-03 09:30:59 -060043#include <timestamp.h>
wdenkc6097192002-11-03 00:24:07 +000044#include <version.h>
45
46#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
47
48#include <ppc_asm.tmpl>
49#include <ppc_defs.h>
50
51#include <asm/cache.h>
52#include <asm/mmu.h>
Peter Tyserd98b0522010-10-14 23:33:24 -050053#include <asm/u-boot.h>
wdenkc6097192002-11-03 00:24:07 +000054
55#ifndef CONFIG_IDENT_STRING
56#define CONFIG_IDENT_STRING ""
57#endif
58
59/* We don't want the MMU yet.
60*/
61#undef MSR_KERNEL
62/* FP, Machine Check and Recoverable Interr. */
63#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
64
65/*
66 * Set up GOT: Global Offset Table
67 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +010068 * Use r12 to access the GOT
wdenkc6097192002-11-03 00:24:07 +000069 */
70 START_GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(_FIXUP_TABLE_)
73
74 GOT_ENTRY(_start)
75 GOT_ENTRY(_start_of_vectors)
76 GOT_ENTRY(_end_of_vectors)
77 GOT_ENTRY(transfer_to_handler)
78
wdenk3b57fe02003-05-30 12:48:29 +000079 GOT_ENTRY(__init_end)
Po-Yu Chuang44c6e652011-03-01 22:59:59 +000080 GOT_ENTRY(__bss_end__)
wdenk5d232d02003-05-22 22:52:13 +000081 GOT_ENTRY(__bss_start)
wdenkc6097192002-11-03 00:24:07 +000082#if defined(CONFIG_FADS)
83 GOT_ENTRY(environment)
84#endif
85 END_GOT
86
87/*
88 * r3 - 1st arg to board_init(): IMMP pointer
89 * r4 - 2nd arg to board_init(): boot flag
90 */
91 .text
92 .long 0x27051956 /* U-Boot Magic Number */
93 .globl version_string
94version_string:
95 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -060096 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenkc6097192002-11-03 00:24:07 +000097 .ascii CONFIG_IDENT_STRING, "\0"
98
99 . = EXC_OFF_SYS_RESET
100 .globl _start
101_start:
wdenkc6097192002-11-03 00:24:07 +0000102 /* Initialize machine status; enable machine check interrupt */
103 /*----------------------------------------------------------------------*/
104 li r3, MSR_KERNEL /* Set FP, ME, RI flags */
105 mtmsr r3
106 mtspr SRR1, r3 /* Make SRR1 match MSR */
107
108 addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
109 mtspr HID0, r0 /* disable I and D caches */
110
111 mfspr r3, ICR /* clear Interrupt Cause Register */
112
113 mfmsr r3 /* turn off address translation */
114 addis r4,0,0xffff
115 ori r4,r4,0xffcf
116 and r3,r3,r4
117 mtmsr r3
118 isync
119 sync /* the MMU should be off... */
120
121
122in_flash:
123#if defined(CONFIG_BMW)
124 bl early_init_f /* Must be ASM: no stack yet! */
125#endif
126 /*
127 * Setup BATs - cannot be done in C since we don't have a stack yet
128 */
129 bl setup_bats
130
131 /* Enable MMU.
132 */
133 mfmsr r3
134 ori r3, r3, (MSR_IR | MSR_DR)
135 mtmsr r3
136#if !defined(CONFIG_BMW)
137 /* Enable and invalidate data cache.
138 */
139 mfspr r3, HID0
140 mr r2, r3
141 ori r3, r3, HID0_DCE | HID0_DCI
142 ori r2, r2, HID0_DCE
143 sync
144 mtspr HID0, r3
145 mtspr HID0, r2
146 sync
147
148 /* Allocate Initial RAM in data cache.
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
151 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
wdenkc6097192002-11-03 00:24:07 +0000152 li r2, 128
153 mtctr r2
1541:
155 dcbz r0, r3
156 addi r3, r3, 32
157 bdnz 1b
158
159 /* Lock way0 in data cache.
160 */
161 mfspr r3, 1011
162 lis r2, 0xffff
163 ori r2, r2, 0xff1f
164 and r3, r3, r2
165 ori r3, r3, 0x0080
166 sync
167 mtspr 1011, r3
168#endif /* !CONFIG_BMW */
169 /*
170 * Thisk the stack pointer *somewhere* sensible. Doesnt
171 * matter much where as we'll move it when we relocate
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
174 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
wdenkc6097192002-11-03 00:24:07 +0000175
176 li r0, 0 /* Make room for stack frame header and */
177 stwu r0, -4(r1) /* clear final stack frame so that */
178 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
179
180 /* let the C-code set up the rest */
181 /* */
182 /* Be careful to keep code relocatable ! */
183 /*----------------------------------------------------------------------*/
184
185 GET_GOT /* initialize GOT access */
Wolfgang Denk8c4734e2011-04-20 22:11:21 +0200186
wdenkc6097192002-11-03 00:24:07 +0000187 /* r3: IMMR */
188 bl cpu_init_f /* run low-level CPU init code (from Flash) */
189
wdenkc6097192002-11-03 00:24:07 +0000190 bl board_init_f /* run 1st part of board init code (from Flash) */
191
Peter Tyser52ebd9c2010-09-14 19:13:53 -0500192 /* NOTREACHED - board_init_f() does not return */
193
wdenkc6097192002-11-03 00:24:07 +0000194
wdenkc6097192002-11-03 00:24:07 +0000195 .globl _start_of_vectors
196_start_of_vectors:
197
198/* Machine check */
199 STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
200
201/* Data Storage exception. "Never" generated on the 860. */
202 STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
203
204/* Instruction Storage exception. "Never" generated on the 860. */
205 STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
206
207/* External Interrupt exception. */
208 STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
209
210/* Alignment exception. */
211 . = EXC_OFF_ALIGN
212Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200213 EXCEPTION_PROLOG(SRR0, SRR1)
wdenkc6097192002-11-03 00:24:07 +0000214 mfspr r4,DAR
215 stw r4,_DAR(r21)
216 mfspr r5,DSISR
217 stw r5,_DSISR(r21)
218 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100219 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
wdenkc6097192002-11-03 00:24:07 +0000220
221/* Program check exception */
222 . = EXC_OFF_PROGRAM
223ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200224 EXCEPTION_PROLOG(SRR0, SRR1)
wdenkc6097192002-11-03 00:24:07 +0000225 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100226 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
227 MSR_KERNEL, COPY_EE)
wdenkc6097192002-11-03 00:24:07 +0000228
229 /* No FPU on MPC8xx. This exception is not supposed to happen.
230 */
231 STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
232
233 /* I guess we could implement decrementer, and may have
234 * to someday for timekeeping.
235 */
236 STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
237 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
238 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000239 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenkc6097192002-11-03 00:24:07 +0000240
241 STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
242
243 STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
244 STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
245
246 STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
247 STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
248 STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
wdenk43d96162003-03-06 00:02:04 +0000249 STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
wdenkc6097192002-11-03 00:24:07 +0000250 STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
251 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
252 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
253 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
254 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
255 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
256 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
257 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
258 STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
259 STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
260 STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
261 STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
262
263 STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
264
265 .globl _end_of_vectors
266_end_of_vectors:
267
268
269 . = 0x3000
270
271/*
272 * This code finishes saving the registers to the exception frame
273 * and jumps to the appropriate handler for the exception.
274 * Register r21 is pointer into trap frame, r1 has new stack pointer.
275 */
276 .globl transfer_to_handler
277transfer_to_handler:
278 stw r22,_NIP(r21)
279 lis r22,MSR_POW@h
280 andc r23,r23,r22
281 stw r23,_MSR(r21)
282 SAVE_GPR(7, r21)
283 SAVE_4GPRS(8, r21)
284 SAVE_8GPRS(12, r21)
285 SAVE_8GPRS(24, r21)
286#if 0
287 andi. r23,r23,MSR_PR
288 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
289 beq 2f
290 addi r24,r1,STACK_FRAME_OVERHEAD
291 stw r24,PT_REGS(r23)
2922: addi r2,r23,-TSS /* set r2 to current */
293 tovirt(r2,r2,r23)
294#endif
295 mflr r23
296 andi. r24,r23,0x3f00 /* get vector offset */
297 stw r24,TRAP(r21)
298 li r22,0
299 stw r22,RESULT(r21)
300 mtspr SPRG2,r22 /* r1 is now kernel sp */
301#if 0
302 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
303 cmplw 0,r1,r2
304 cmplw 1,r1,r24
305 crand 1,1,4
306 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
307#endif
308 lwz r24,0(r23) /* virtual address of handler */
309 lwz r23,4(r23) /* where to go when done */
310 mtspr SRR0,r24
311 ori r20,r20,0x30 /* enable IR, DR */
312 mtspr SRR1,r20
313 mtlr r23
314 SYNC
315 rfi /* jump to handler, enable MMU */
316
317int_return:
318 mfmsr r28 /* Disable interrupts */
319 li r4,0
320 ori r4,r4,MSR_EE
321 andc r28,r28,r4
322 SYNC /* Some chip revs need this... */
323 mtmsr r28
324 SYNC
325 lwz r2,_CTR(r1)
326 lwz r0,_LINK(r1)
327 mtctr r2
328 mtlr r0
329 lwz r2,_XER(r1)
330 lwz r0,_CCR(r1)
331 mtspr XER,r2
332 mtcrf 0xFF,r0
333 REST_10GPRS(3, r1)
334 REST_10GPRS(13, r1)
335 REST_8GPRS(23, r1)
336 REST_GPR(31, r1)
337 lwz r2,_NIP(r1) /* Restore environment */
338 lwz r0,_MSR(r1)
339 mtspr SRR0,r2
340 mtspr SRR1,r0
341 lwz r0,GPR0(r1)
342 lwz r2,GPR2(r1)
343 lwz r1,GPR1(r1)
344 SYNC
345 rfi
346
347/* Cache functions.
348*/
349 .globl icache_enable
350icache_enable:
351 mfspr r5,HID0 /* turn on the I cache. */
352 ori r5,r5,0x8800 /* Instruction cache only! */
353 addis r6,0,0xFFFF
354 ori r6,r6,0xF7FF
355 and r6,r5,r6 /* clear the invalidate bit */
356 sync
357 mtspr HID0,r5
358 mtspr HID0,r6
359 isync
360 sync
361 blr
362
363 .globl icache_disable
364icache_disable:
365 mfspr r5,HID0
366 addis r6,0,0xFFFF
367 ori r6,r6,0x7FFF
368 and r5,r5,r6
369 sync
370 mtspr HID0,r5
371 isync
372 sync
373 blr
374
375 .globl icache_status
376icache_status:
377 mfspr r3, HID0
378 srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
379 andi. r3, r3, 1
380 blr
381
382 .globl dcache_enable
383dcache_enable:
384 mfspr r5,HID0 /* turn on the D cache. */
385 ori r5,r5,0x4400 /* Data cache only! */
386 mfspr r4, PVR /* read PVR */
387 srawi r3, r4, 16 /* shift off the least 16 bits */
388 cmpi 0, 0, r3, 0xC /* Check for Max pvr */
389 bne NotMax
390 ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
391NotMax:
392 addis r6,0,0xFFFF
393 ori r6,r6,0xFBFF
394 and r6,r5,r6 /* clear the invalidate bit */
395 sync
396 mtspr HID0,r5
397 mtspr HID0,r6
398 isync
399 sync
400 blr
401
402 .globl dcache_disable
403dcache_disable:
404 mfspr r5,HID0
405 addis r6,0,0xFFFF
406 ori r6,r6,0xBFFF
407 and r5,r5,r6
408 sync
409 mtspr HID0,r5
410 isync
411 sync
412 blr
413
414 .globl dcache_status
415dcache_status:
416 mfspr r3, HID0
417 srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
418 andi. r3, r3, 1
419 blr
420
421 .globl dc_read
422dc_read:
423/*TODO : who uses this, what should it do?
424*/
425 blr
426
427
428 .globl get_pvr
429get_pvr:
430 mfspr r3, PVR
431 blr
432
433
434/*------------------------------------------------------------------------------*/
435
436/*
437 * void relocate_code (addr_sp, gd, addr_moni)
438 *
439 * This "function" does not return, instead it continues in RAM
440 * after relocating the monitor code.
441 *
442 * r3 = dest
443 * r4 = src
444 * r5 = length in bytes
445 * r6 = cachelinesize
446 */
447 .globl relocate_code
448relocate_code:
449
450 mr r1, r3 /* Set new stack pointer */
451 mr r9, r4 /* Save copy of Global Data pointer */
452 mr r10, r5 /* Save copy of Destination Address */
453
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100454 GET_GOT
wdenkc6097192002-11-03 00:24:07 +0000455 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#ifdef CONFIG_SYS_RAMBOOT
457 lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */
458 ori r4, r4, CONFIG_SYS_SDRAM_BASE@l
wdenkc6097192002-11-03 00:24:07 +0000459#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
461 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenkc6097192002-11-03 00:24:07 +0000462#endif
wdenk3b57fe02003-05-30 12:48:29 +0000463 lwz r5, GOT(__init_end)
464 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenkc6097192002-11-03 00:24:07 +0000466
467 /*
468 * Fix GOT pointer:
469 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenkc6097192002-11-03 00:24:07 +0000471 *
472 * Offset:
473 */
474 sub r15, r10, r4
475
476 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100477 add r12, r12, r15
wdenkc6097192002-11-03 00:24:07 +0000478 /* the the one used by the C code */
479 add r30, r30, r15
480
481 /*
482 * Now relocate code
483 */
484
485 cmplw cr1,r3,r4
486 addi r0,r5,3
487 srwi. r0,r0,2
488 beq cr1,4f /* In place copy is not necessary */
489 beq 7f /* Protect against 0 count */
490 mtctr r0
491 bge cr1,2f
492
493 la r8,-4(r4)
494 la r7,-4(r3)
4951: lwzu r0,4(r8)
496 stwu r0,4(r7)
497 bdnz 1b
498 b 4f
499
5002: slwi r0,r0,2
501 add r8,r4,r0
502 add r7,r3,r0
5033: lwzu r0,-4(r8)
504 stwu r0,-4(r7)
505 bdnz 3b
506
wdenk7205e402003-09-10 22:30:53 +00005074:
508#if !defined(CONFIG_BMW)
509/* Unlock the data cache and invalidate locked area */
510 xor r0, r0, r0
511 mtspr 1011, r0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512 lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
513 ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
wdenk7205e402003-09-10 22:30:53 +0000514 li r0, 128
515 mtctr r0
51641:
517 dcbi r0, r4
518 addi r4, r4, 32
519 bdnz 41b
520#endif
521
wdenkc6097192002-11-03 00:24:07 +0000522/*
523 * Now flush the cache: note that we must start from a cache aligned
524 * address. Otherwise we might miss one cache line.
525 */
wdenk7205e402003-09-10 22:30:53 +0000526 cmpwi r6,0
wdenkc6097192002-11-03 00:24:07 +0000527 add r5,r3,r5
528 beq 7f /* Always flush prefetch queue in any case */
529 subi r0,r6,1
530 andc r3,r3,r0
531 mr r4,r3
5325: dcbst 0,r4
533 add r4,r4,r6
534 cmplw r4,r5
535 blt 5b
536 sync /* Wait for all dcbst to complete on bus */
537 mr r4,r3
5386: icbi 0,r4
539 add r4,r4,r6
540 cmplw r4,r5
541 blt 6b
5427: sync /* Wait for all icbi to complete on bus */
543 isync
544
545/*
546 * We are done. Do not return, instead branch to second part of board
547 * initialization, now running from RAM.
548 */
549
550 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
551 mtlr r0
552 blr
553
554in_ram:
555
556 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100557 * Relocation Function, r12 point to got2+0x8000
wdenkc6097192002-11-03 00:24:07 +0000558 *
559 * Adjust got2 pointers, no need to check for 0, this code
560 * already puts a few entries in the table.
561 */
562 li r0,__got2_entries@sectoff@l
563 la r3,GOT(_GOT2_TABLE_)
564 lwz r11,GOT(_GOT2_TABLE_)
565 mtctr r0
566 sub r11,r3,r11
567 addi r3,r3,-4
5681: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200569 cmpwi r0,0
570 beq- 2f
wdenkc6097192002-11-03 00:24:07 +0000571 add r0,r0,r11
572 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02005732: bdnz 1b
wdenkc6097192002-11-03 00:24:07 +0000574
575 /*
576 * Now adjust the fixups and the pointers to the fixups
577 * in case we need to move ourselves again.
578 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200579 li r0,__fixup_entries@sectoff@l
wdenkc6097192002-11-03 00:24:07 +0000580 lwz r3,GOT(_FIXUP_TABLE_)
581 cmpwi r0,0
582 mtctr r0
583 addi r3,r3,-4
584 beq 4f
5853: lwzu r4,4(r3)
586 lwzux r0,r4,r11
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200587 cmpwi r0,0
wdenkc6097192002-11-03 00:24:07 +0000588 add r0,r0,r11
Joakim Tjernlund34bbf612010-11-04 19:02:00 +0100589 stw r4,0(r3)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200590 beq- 5f
wdenkc6097192002-11-03 00:24:07 +0000591 stw r0,0(r4)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +02005925: bdnz 3b
wdenkc6097192002-11-03 00:24:07 +00005934:
594clear_bss:
595 /*
596 * Now clear BSS segment
597 */
wdenk5d232d02003-05-22 22:52:13 +0000598 lwz r3,GOT(__bss_start)
Po-Yu Chuang44c6e652011-03-01 22:59:59 +0000599 lwz r4,GOT(__bss_end__)
wdenkc6097192002-11-03 00:24:07 +0000600
601 cmplw 0, r3, r4
602 beq 6f
603
604 li r0, 0
6055:
606 stw r0, 0(r3)
607 addi r3, r3, 4
608 cmplw 0, r3, r4
609 blt 5b
6106:
611
612 mr r3, r9 /* Global Data pointer */
613 mr r4, r10 /* Destination Address */
614 bl board_init_r
615
wdenkc6097192002-11-03 00:24:07 +0000616 /*
617 * Copy exception vector code to low memory
618 *
619 * r3: dest_addr
620 * r7: source address, r8: end address, r9: target address
621 */
622 .globl trap_init
623trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100624 mflr r4 /* save link register */
625 GET_GOT
wdenkc6097192002-11-03 00:24:07 +0000626 lwz r7, GOT(_start)
627 lwz r8, GOT(_end_of_vectors)
628
wdenk682011f2003-06-03 23:54:09 +0000629 li r9, 0x100 /* reset vector always at 0x100 */
wdenkc6097192002-11-03 00:24:07 +0000630
631 cmplw 0, r7, r8
632 bgelr /* return if r7>=r8 - just in case */
wdenkc6097192002-11-03 00:24:07 +00006331:
634 lwz r0, 0(r7)
635 stw r0, 0(r9)
636 addi r7, r7, 4
637 addi r9, r9, 4
638 cmplw 0, r7, r8
639 bne 1b
640
641 /*
642 * relocate `hdlr' and `int_return' entries
643 */
644 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
645 li r8, Alignment - _start + EXC_OFF_SYS_RESET
6462:
647 bl trap_reloc
648 addi r7, r7, 0x100 /* next exception vector */
649 cmplw 0, r7, r8
650 blt 2b
651
652 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
653 bl trap_reloc
654
655 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
656 bl trap_reloc
657
658 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
659 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
6603:
661 bl trap_reloc
662 addi r7, r7, 0x100 /* next exception vector */
663 cmplw 0, r7, r8
664 blt 3b
665
666 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
667 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6684:
669 bl trap_reloc
670 addi r7, r7, 0x100 /* next exception vector */
671 cmplw 0, r7, r8
672 blt 4b
673
674 mtlr r4 /* restore link register */
675 blr
676
wdenkc6097192002-11-03 00:24:07 +0000677 /* Setup the BAT registers.
678 */
679setup_bats:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200680 lis r4, CONFIG_SYS_IBAT0L@h
681 ori r4, r4, CONFIG_SYS_IBAT0L@l
682 lis r3, CONFIG_SYS_IBAT0U@h
683 ori r3, r3, CONFIG_SYS_IBAT0U@l
wdenkc6097192002-11-03 00:24:07 +0000684 mtspr IBAT0L, r4
685 mtspr IBAT0U, r3
686 isync
687
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200688 lis r4, CONFIG_SYS_DBAT0L@h
689 ori r4, r4, CONFIG_SYS_DBAT0L@l
690 lis r3, CONFIG_SYS_DBAT0U@h
691 ori r3, r3, CONFIG_SYS_DBAT0U@l
wdenkc6097192002-11-03 00:24:07 +0000692 mtspr DBAT0L, r4
693 mtspr DBAT0U, r3
694 isync
695
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200696 lis r4, CONFIG_SYS_IBAT1L@h
697 ori r4, r4, CONFIG_SYS_IBAT1L@l
698 lis r3, CONFIG_SYS_IBAT1U@h
699 ori r3, r3, CONFIG_SYS_IBAT1U@l
wdenkc6097192002-11-03 00:24:07 +0000700 mtspr IBAT1L, r4
701 mtspr IBAT1U, r3
702 isync
703
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200704 lis r4, CONFIG_SYS_DBAT1L@h
705 ori r4, r4, CONFIG_SYS_DBAT1L@l
706 lis r3, CONFIG_SYS_DBAT1U@h
707 ori r3, r3, CONFIG_SYS_DBAT1U@l
wdenkc6097192002-11-03 00:24:07 +0000708 mtspr DBAT1L, r4
709 mtspr DBAT1U, r3
710 isync
711
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200712 lis r4, CONFIG_SYS_IBAT2L@h
713 ori r4, r4, CONFIG_SYS_IBAT2L@l
714 lis r3, CONFIG_SYS_IBAT2U@h
715 ori r3, r3, CONFIG_SYS_IBAT2U@l
wdenkc6097192002-11-03 00:24:07 +0000716 mtspr IBAT2L, r4
717 mtspr IBAT2U, r3
718 isync
719
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200720 lis r4, CONFIG_SYS_DBAT2L@h
721 ori r4, r4, CONFIG_SYS_DBAT2L@l
722 lis r3, CONFIG_SYS_DBAT2U@h
723 ori r3, r3, CONFIG_SYS_DBAT2U@l
wdenkc6097192002-11-03 00:24:07 +0000724 mtspr DBAT2L, r4
725 mtspr DBAT2U, r3
726 isync
727
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200728 lis r4, CONFIG_SYS_IBAT3L@h
729 ori r4, r4, CONFIG_SYS_IBAT3L@l
730 lis r3, CONFIG_SYS_IBAT3U@h
731 ori r3, r3, CONFIG_SYS_IBAT3U@l
wdenkc6097192002-11-03 00:24:07 +0000732 mtspr IBAT3L, r4
733 mtspr IBAT3U, r3
734 isync
735
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200736 lis r4, CONFIG_SYS_DBAT3L@h
737 ori r4, r4, CONFIG_SYS_DBAT3L@l
738 lis r3, CONFIG_SYS_DBAT3U@h
739 ori r3, r3, CONFIG_SYS_DBAT3U@l
wdenkc6097192002-11-03 00:24:07 +0000740 mtspr DBAT3L, r4
741 mtspr DBAT3U, r3
742 isync
743
744 /* Invalidate TLBs.
745 * -> for (val = 0; val < 0x20000; val+=0x1000)
746 * -> tlbie(val);
747 */
748 lis r3, 0
749 lis r5, 2
750
7511:
752 tlbie r3
753 addi r3, r3, 0x1000
754 cmp 0, 0, r3, r5
755 blt 1b
756
757 blr