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TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew8e585f02007-06-18 13:50:13 -05008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5329EVB_H
15#define _M5329EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChung Liew8e585f02007-06-18 13:50:13 -050021
TsiChungLiew9998bd32007-08-05 03:19:10 -050022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew8e585f02007-06-18 13:50:13 -050024#define CONFIG_BAUDRATE 115200
TsiChung Liew8e585f02007-06-18 13:50:13 -050025
26#undef CONFIG_WATCHDOG
27#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
28
TsiChungLiewab77bc52007-08-15 15:39:17 -050029/* Command line configuration */
30#include <config_cmd_default.h>
31
32#define CONFIG_CMD_CACHE
33#define CONFIG_CMD_DATE
34#define CONFIG_CMD_ELF
35#define CONFIG_CMD_FLASH
36#define CONFIG_CMD_I2C
37#define CONFIG_CMD_MEMORY
38#define CONFIG_CMD_MISC
39#define CONFIG_CMD_MII
40#define CONFIG_CMD_NET
41#define CONFIG_CMD_PING
42#define CONFIG_CMD_REGINFO
TsiChung0dca8742007-07-10 15:45:43 -050043
stany MARCEL96d94382011-10-19 00:17:13 +080044#ifdef CONFIG_NANDFLASH_SIZE
TsiChungLiewab77bc52007-08-15 15:39:17 -050045# define CONFIG_CMD_NAND
TsiChungLiew1a33ce62007-08-05 04:31:18 -050046#endif
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_UNIFY_CACHE
TsiChung Liew8e585f02007-06-18 13:50:13 -050049
50#define CONFIG_MCFFEC
51#ifdef CONFIG_MCFFEC
TsiChung Liew8e585f02007-06-18 13:50:13 -050052# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050053# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054# define CONFIG_SYS_DISCOVER_PHY
55# define CONFIG_SYS_RX_ETH_BUFFER 8
56# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew8e585f02007-06-18 13:50:13 -050057
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058# define CONFIG_SYS_FEC0_PINMUX 0
59# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
62# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liew8e585f02007-06-18 13:50:13 -050063# define FECDUPLEX FULL
64# define FECSPEED _100BASET
65# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
67# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew8e585f02007-06-18 13:50:13 -050068# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liew8e585f02007-06-18 13:50:13 -050070#endif
71
TsiChung Liew8e585f02007-06-18 13:50:13 -050072#define CONFIG_MCFRTC
TsiChungLiew48dbfea2007-07-05 22:39:07 -050073#undef RTC_DEBUG
TsiChung Liew8e585f02007-06-18 13:50:13 -050074
75/* Timer */
76#define CONFIG_MCFTMR
TsiChung Liew8e585f02007-06-18 13:50:13 -050077#undef CONFIG_MCFPIT
TsiChung Liew8e585f02007-06-18 13:50:13 -050078
TsiChungLieweaf9e442007-08-05 04:11:20 -050079/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020080#define CONFIG_SYS_I2C
81#define CONFIG_SYS_I2C_FSL
82#define CONFIG_SYS_FSL_I2C_SPEED 80000
83#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
84#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLieweaf9e442007-08-05 04:11:20 -050086
TsiChung Liew8e585f02007-06-18 13:50:13 -050087#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
TsiChungLiewab77bc52007-08-15 15:39:17 -050088#define CONFIG_UDP_CHECKSUM
89
TsiChung Liew8e585f02007-06-18 13:50:13 -050090#ifdef CONFIG_MCFFEC
TsiChungLieweaf9e442007-08-05 04:11:20 -050091# define CONFIG_IPADDR 192.162.1.2
92# define CONFIG_NETMASK 255.255.255.0
93# define CONFIG_SERVERIP 192.162.1.1
TsiChung Liew8e585f02007-06-18 13:50:13 -050094# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liew8e585f02007-06-18 13:50:13 -050095#endif /* FEC_ENET */
96
97#define CONFIG_HOSTNAME M5329EVB
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "loadaddr=40010000\0" \
101 "u-boot=u-boot.bin\0" \
102 "load=tftp ${loadaddr) ${u-boot}\0" \
103 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +0800104 "prog=prot off 0 3ffff;" \
105 "era 0 3ffff;" \
TsiChung Liew8e585f02007-06-18 13:50:13 -0500106 "cp.b ${loadaddr} 0 ${filesize};" \
107 "save\0" \
108 ""
109
TsiChungLieweaf9e442007-08-05 04:11:20 -0500110#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_PROMPT "-> "
112#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500113
TsiChungLiewab77bc52007-08-15 15:39:17 -0500114#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500116#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500118#endif
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
123#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CLK 80000000
126#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChung Liew8e585f02007-06-18 13:50:13 -0500127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiew1a33ce62007-08-05 04:31:18 -0500131
TsiChung Liew8e585f02007-06-18 13:50:13 -0500132/*
133 * Low Level Configuration Settings
134 * (address mappings, register initial values, etc.)
135 * You should know what you are doing if you make changes here.
136 */
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area (in DPRAM)
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200141#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200143#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liew8e585f02007-06-18 13:50:13 -0500145
146/*-----------------------------------------------------------------------
147 * Start addresses for the final memory configuration
148 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_SDRAM_BASE 0x40000000
152#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
153#define CONFIG_SYS_SDRAM_CFG1 0x53722730
154#define CONFIG_SYS_SDRAM_CFG2 0x56670000
155#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
156#define CONFIG_SYS_SDRAM_EMOD 0x40010000
157#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
160#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
163#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
166#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500167
168/*
169 * For booting Linux, the board info and command line data
170 * have to be in the first 8 MB of memory, since this is
171 * the maximum mapped by the Linux kernel during initialization ??
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000174#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500175
176/*-----------------------------------------------------------------------
177 * FLASH organization
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_CFI
180#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200181# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
183# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
184# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
186# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500187#endif
188
stany MARCEL96d94382011-10-19 00:17:13 +0800189#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190# define CONFIG_SYS_MAX_NAND_DEVICE 1
191# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
192# define CONFIG_SYS_NAND_SIZE 1
193# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewab77bc52007-08-15 15:39:17 -0500194# define NAND_ALLOW_ERASE_ALL 1
195# define CONFIG_JFFS2_NAND 1
196# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewab77bc52007-08-15 15:39:17 -0500198# define CONFIG_JFFS2_PART_OFFSET 0x00000000
TsiChungLiew1a33ce62007-08-05 04:31:18 -0500199#endif
200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -0500202
203/* Configuration for environment
204 * Environment is embedded in u-boot in the second sector of the flash
205 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200206#define CONFIG_ENV_OFFSET 0x4000
207#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200208#define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500209
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200210#define LDS_BOARD_TEXT \
211 . = DEFINED(env_offset) ? env_offset : .; \
212 common/env_embedded.o (.text*);
213
TsiChung Liew8e585f02007-06-18 13:50:13 -0500214/*-----------------------------------------------------------------------
215 * Cache Configuration
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew8e585f02007-06-18 13:50:13 -0500218
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600219#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200220 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600221#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200222 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600223#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
224#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
225 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
226 CF_ACR_EN | CF_ACR_SM_ALL)
227#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
228 CF_CACR_DCM_P)
229
TsiChung Liew8e585f02007-06-18 13:50:13 -0500230/*-----------------------------------------------------------------------
231 * Chipselect bank definitions
232 */
233/*
234 * CS0 - NOR Flash 1, 2, 4, or 8MB
235 * CS1 - CompactFlash and registers
236 * CS2 - NAND Flash 16, 32, or 64MB
237 * CS3 - Available
238 * CS4 - Available
239 * CS5 - Available
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CS0_BASE 0
242#define CONFIG_SYS_CS0_MASK 0x007f0001
243#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_CS1_BASE 0x10000000
246#define CONFIG_SYS_CS1_MASK 0x001f0001
247#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChung Liew8e585f02007-06-18 13:50:13 -0500248
stany MARCEL96d94382011-10-19 00:17:13 +0800249#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_CS2_BASE 0x20000000
stany MARCEL96d94382011-10-19 00:17:13 +0800251#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChung Liew8e585f02007-06-18 13:50:13 -0500253#endif
254
TsiChung Liew8e585f02007-06-18 13:50:13 -0500255#endif /* _M5329EVB_H */