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gerrit.cesnet.cz / github / trini / u-boot / 74336f7daa4b1a45d04ddc9ef05737af54ae4836 / . / arch / arm / dts / rk3288.dtsi
blob: fb1d1f7e1b01ff6e5208ed77cf5168cd58ef75e4 [file] [log] [blame]
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3288-cru.h>
10#include <dt-bindings/power-domain/rk3288.h>
11#include <dt-bindings/thermal/thermal.h>
12#include "skeleton.dtsi"
13
14/ {
15 compatible = "rockchip,rk3288";
16
17 interrupt-parent = <&gic>;
18 aliases {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 gpio4 = &gpio4;
24 gpio5 = &gpio5;
25 gpio6 = &gpio6;
26 gpio7 = &gpio7;
27 gpio8 = &gpio8;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
31 i2c3 = &i2c3;
32 i2c4 = &i2c4;
33 i2c5 = &i2c5;
34 mmc0 = &emmc;
35 mmc1 = &sdmmc;
36 mmc2 = &sdio0;
37 mmc3 = &sdio1;
38 mshc0 = &emmc;
39 mshc1 = &sdmmc;
40 mshc2 = &sdio0;
41 mshc3 = &sdio1;
42 serial0 = &uart0;
43 serial1 = &uart1;
44 serial2 = &uart2;
45 serial3 = &uart3;
46 serial4 = &uart4;
47 spi0 = &spi0;
48 spi1 = &spi1;
49 spi2 = &spi2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
57
58 cpu0: cpu@500 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x500>;
62 operating-points = <
63 /* KHz uV */
64 1800000 1400000
65 1704000 1350000
66 1608000 1300000
67 1512000 1250000
68 1416000 1200000
69 1200000 1100000
70 1008000 1050000
71 816000 1000000
72 696000 950000
73 600000 900000
74 408000 900000
75 216000 900000
76 126000 900000
77 >;
78 #cooling-cells = <2>; /* min followed by max */
79 clock-latency = <40000>;
80 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE0>;
82 };
83 cpu@501 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x501>;
87 resets = <&cru SRST_CORE1>;
88 };
89 cpu@502 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x502>;
93 resets = <&cru SRST_CORE2>;
94 };
95 cpu@503 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a12";
98 reg = <0x503>;
99 resets = <&cru SRST_CORE3>;
100 };
101 };
102
103 amba {
104 compatible = "arm,amba-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges;
108
109 dmac_peri: dma-controller@ff250000 {
110 compatible = "arm,pl330", "arm,primecell";
111 broken-no-flushp;
112 reg = <0xff250000 0x4000>;
113 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
115 #dma-cells = <1>;
116 clocks = <&cru ACLK_DMAC2>;
117 clock-names = "apb_pclk";
118 };
119
120 dmac_bus_ns: dma-controller@ff600000 {
121 compatible = "arm,pl330", "arm,primecell";
122 broken-no-flushp;
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 #dma-cells = <1>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
129 status = "disabled";
130 };
131
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
134 broken-no-flushp;
135 reg = <0xffb20000 0x4000>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 #dma-cells = <1>;
139 clocks = <&cru ACLK_DMAC1>;
140 clock-names = "apb_pclk";
141 };
142 };
143
144 xin24m: oscillator {
145 compatible = "fixed-clock";
146 clock-frequency = <24000000>;
147 clock-output-names = "xin24m";
148 #clock-cells = <0>;
149 };
150
151 timer {
152 arm,use-physical-timer;
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
158 clock-frequency = <24000000>;
159 always-on;
160 };
161
162 display-subsystem {
163 compatible = "rockchip,display-subsystem";
164 ports = <&vopl_out>, <&vopb_out>;
165 };
166
167 sdmmc: dwmmc@ff0c0000 {
168 compatible = "rockchip,rk3288-dw-mshc";
169 clock-freq-min-max = <400000 150000000>;
170 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
171 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
172 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
173 fifo-depth = <0x100>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0xff0c0000 0x4000>;
176 status = "disabled";
177 };
178
179 sdio0: dwmmc@ff0d0000 {
180 compatible = "rockchip,rk3288-dw-mshc";
181 clock-freq-min-max = <400000 150000000>;
182 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
183 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
184 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
185 fifo-depth = <0x100>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 reg = <0xff0d0000 0x4000>;
188 status = "disabled";
189 };
190
191 sdio1: dwmmc@ff0e0000 {
192 compatible = "rockchip,rk3288-dw-mshc";
193 clock-freq-min-max = <400000 150000000>;
194 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
195 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
196 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
197 fifo-depth = <0x100>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0xff0e0000 0x4000>;
200 status = "disabled";
201 };
202
203 emmc: dwmmc@ff0f0000 {
204 compatible = "rockchip,rk3288-dw-mshc";
205 clock-freq-min-max = <400000 150000000>;
206 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
207 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
208 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
209 fifo-depth = <0x100>;
210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
211 reg = <0xff0f0000 0x4000>;
212 status = "disabled";
213 };
214
215 saradc: saradc@ff100000 {
216 compatible = "rockchip,saradc";
217 reg = <0xff100000 0x100>;
218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
219 #io-channel-cells = <1>;
220 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
221 clock-names = "saradc", "apb_pclk";
222 status = "disabled";
223 };
224
225 spi0: spi@ff110000 {
226 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
227 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
228 clock-names = "spiclk", "apb_pclk";
229 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
230 dma-names = "tx", "rx";
231 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
234 reg = <0xff110000 0x1000>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 status = "disabled";
238 };
239
240 spi1: spi@ff120000 {
241 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
242 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
243 clock-names = "spiclk", "apb_pclk";
244 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
245 dma-names = "tx", "rx";
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 reg = <0xff120000 0x1000>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 spi2: spi@ff130000 {
256 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
258 clock-names = "spiclk", "apb_pclk";
259 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
260 dma-names = "tx", "rx";
261 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
264 reg = <0xff130000 0x1000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 i2c1: i2c@ff140000 {
271 compatible = "rockchip,rk3288-i2c";
272 reg = <0xff140000 0x1000>;
273 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 clock-names = "i2c";
277 clocks = <&cru PCLK_I2C1>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c1_xfer>;
280 status = "disabled";
281 };
282
283 i2c3: i2c@ff150000 {
284 compatible = "rockchip,rk3288-i2c";
285 reg = <0xff150000 0x1000>;
286 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clock-names = "i2c";
290 clocks = <&cru PCLK_I2C3>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c3_xfer>;
293 status = "disabled";
294 };
295
296 i2c4: i2c@ff160000 {
297 compatible = "rockchip,rk3288-i2c";
298 reg = <0xff160000 0x1000>;
299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 clock-names = "i2c";
303 clocks = <&cru PCLK_I2C4>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c4_xfer>;
306 status = "disabled";
307 };
308
309 i2c5: i2c@ff170000 {
310 compatible = "rockchip,rk3288-i2c";
311 reg = <0xff170000 0x1000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 clock-names = "i2c";
316 clocks = <&cru PCLK_I2C5>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&i2c5_xfer>;
319 status = "disabled";
320 };
321 uart0: serial@ff180000 {
322 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
323 reg = <0xff180000 0x100>;
324 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
325 reg-shift = <2>;
326 reg-io-width = <4>;
Thomas Chou98a51fc2015-11-19 21:48:08 +0800[diff] [blame]327 clock-frequency = <24000000>;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
329 clock-names = "baudclk", "apb_pclk";
330 pinctrl-names = "default";
331 pinctrl-0 = <&uart0_xfer>;
332 status = "disabled";
333 };
334
335 uart1: serial@ff190000 {
336 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
337 reg = <0xff190000 0x100>;
338 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
339 reg-shift = <2>;
340 reg-io-width = <4>;
Thomas Chou98a51fc2015-11-19 21:48:08 +0800[diff] [blame]341 clock-frequency = <24000000>;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]342 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
343 clock-names = "baudclk", "apb_pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart1_xfer>;
346 status = "disabled";
347 };
348
349 uart2: serial@ff690000 {
350 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
351 reg = <0xff690000 0x100>;
352 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
353 reg-shift = <2>;
354 reg-io-width = <4>;
Thomas Chou98a51fc2015-11-19 21:48:08 +0800[diff] [blame]355 clock-frequency = <24000000>;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]356 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart2_xfer>;
360 status = "disabled";
361 };
362 uart3: serial@ff1b0000 {
363 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
364 reg = <0xff1b0000 0x100>;
365 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
366 reg-shift = <2>;
367 reg-io-width = <4>;
Thomas Chou98a51fc2015-11-19 21:48:08 +0800[diff] [blame]368 clock-frequency = <24000000>;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]369 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
370 clock-names = "baudclk", "apb_pclk";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart3_xfer>;
373 status = "disabled";
374 };
375
376 uart4: serial@ff1c0000 {
377 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
378 reg = <0xff1c0000 0x100>;
379 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
380 reg-shift = <2>;
381 reg-io-width = <4>;
Thomas Chou98a51fc2015-11-19 21:48:08 +0800[diff] [blame]382 clock-frequency = <24000000>;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]383 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
384 clock-names = "baudclk", "apb_pclk";
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart4_xfer>;
387 status = "disabled";
388 };
389 thermal: thermal-zones {
390 #include "rk3288-thermal.dtsi"
391 };
392
393 tsadc: tsadc@ff280000 {
394 compatible = "rockchip,rk3288-tsadc";
395 reg = <0xff280000 0x100>;
396 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
398 clock-names = "tsadc", "apb_pclk";
399 resets = <&cru SRST_TSADC>;
400 reset-names = "tsadc-apb";
401 pinctrl-names = "otp_out";
402 pinctrl-0 = <&otp_out>;
403 #thermal-sensor-cells = <1>;
404 hw-shut-temp = <125000>;
405 status = "disabled";
406 };
407
408 gmac: ethernet@ff290000 {
409 compatible = "rockchip,rk3288-gmac";
410 reg = <0xff290000 0x10000>;
411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "macirq";
413 rockchip,grf = <&grf>;
414 clocks = <&cru SCLK_MAC>,
415 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
416 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
417 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
418 clock-names = "stmmaceth",
419 "mac_clk_rx", "mac_clk_tx",
420 "clk_mac_ref", "clk_mac_refout",
421 "aclk_mac", "pclk_mac";
422 };
423
424 usb_host0_ehci: usb@ff500000 {
425 compatible = "generic-ehci";
426 reg = <0xff500000 0x100>;
427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru HCLK_USBHOST0>;
429 clock-names = "usbhost";
430 phys = <&usbphy1>;
431 phy-names = "usb";
432 status = "disabled";
433 };
434
435 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
436
437 usb_host1: usb@ff540000 {
438 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
439 "snps,dwc2";
440 reg = <0xff540000 0x40000>;
441 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru HCLK_USBHOST1>;
443 clock-names = "otg";
444 phys = <&usbphy2>;
445 phy-names = "usb2-phy";
446 status = "disabled";
447 };
448
449 usb_otg: usb@ff580000 {
450 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
451 "snps,dwc2";
452 reg = <0xff580000 0x40000>;
453 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru HCLK_OTG0>;
455 clock-names = "otg";
456 phys = <&usbphy0>;
457 phy-names = "usb2-phy";
458 status = "disabled";
459 };
460
461 usb_hsic: usb@ff5c0000 {
462 compatible = "generic-ehci";
463 reg = <0xff5c0000 0x100>;
464 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_HSIC>;
466 clock-names = "usbhost";
467 status = "disabled";
468 };
469
470 dmc: dmc@ff610000 {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]471 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]472 compatible = "rockchip,rk3288-dmc", "syscon";
473 rockchip,cru = <&cru>;
474 rockchip,grf = <&grf>;
475 rockchip,pmu = <&pmu>;
476 rockchip,sgrf = <&sgrf>;
477 rockchip,noc = <&noc>;
478 reg = <0xff610000 0x3fc
479 0xff620000 0x294
480 0xff630000 0x3fc
481 0xff640000 0x294>;
482 rockchip,sram = <&ddr_sram>;
483 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
484 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
485 <&cru ARMCLK>;
486 clock-names = "pclk_ddrupctl0", "pclk_publ0",
487 "pclk_ddrupctl1", "pclk_publ1",
488 "arm_clk";
489 };
490
491 i2c0: i2c@ff650000 {
492 compatible = "rockchip,rk3288-i2c";
493 reg = <0xff650000 0x1000>;
494 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clock-names = "i2c";
498 clocks = <&cru PCLK_I2C0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c0_xfer>;
501 status = "disabled";
502 };
503
504 i2c2: i2c@ff660000 {
505 compatible = "rockchip,rk3288-i2c";
506 reg = <0xff660000 0x1000>;
507 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clock-names = "i2c";
511 clocks = <&cru PCLK_I2C2>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c2_xfer>;
514 status = "disabled";
515 };
516
517 pwm0: pwm@ff680000 {
518 compatible = "rockchip,rk3288-pwm";
519 reg = <0xff680000 0x10>;
520 #pwm-cells = <3>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pwm0_pin>;
523 clocks = <&cru PCLK_PWM>;
524 clock-names = "pwm";
525 rockchip,grf = <&grf>;
526 status = "disabled";
527 };
528
529 pwm1: pwm@ff680010 {
530 compatible = "rockchip,rk3288-pwm";
531 reg = <0xff680010 0x10>;
532 #pwm-cells = <3>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm1_pin>;
535 clocks = <&cru PCLK_PWM>;
536 clock-names = "pwm";
537 rockchip,grf = <&grf>;
538 status = "disabled";
539 };
540
541 pwm2: pwm@ff680020 {
542 compatible = "rockchip,rk3288-pwm";
543 reg = <0xff680020 0x10>;
544 #pwm-cells = <3>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pwm2_pin>;
547 clocks = <&cru PCLK_PWM>;
548 clock-names = "pwm";
549 rockchip,grf = <&grf>;
550 status = "disabled";
551 };
552
553 pwm3: pwm@ff680030 {
554 compatible = "rockchip,rk3288-pwm";
555 reg = <0xff680030 0x10>;
556 #pwm-cells = <2>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm3_pin>;
559 clocks = <&cru PCLK_PWM>;
560 clock-names = "pwm";
561 rockchip,grf = <&grf>;
562 status = "disabled";
563 };
564
565 bus_intmem@ff700000 {
566 compatible = "mmio-sram";
567 reg = <0xff700000 0x18000>;
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0 0xff700000 0x18000>;
571 smp-sram@0 {
572 compatible = "rockchip,rk3066-smp-sram";
573 reg = <0x00 0x10>;
574 };
575 ddr_sram: ddr-sram@1000 {
576 compatible = "rockchip,rk3288-ddr-sram";
577 reg = <0x1000 0x4000>;
578 };
579 };
580
581 sram@ff720000 {
582 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
583 reg = <0xff720000 0x1000>;
584 };
585
586 pmu: power-management@ff730000 {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]587 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]588 compatible = "rockchip,rk3288-pmu", "syscon";
589 reg = <0xff730000 0x100>;
590 };
591
592 sgrf: syscon@ff740000 {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]593 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]594 compatible = "rockchip,rk3288-sgrf", "syscon";
595 reg = <0xff740000 0x1000>;
596 };
597
598 cru: clock-controller@ff760000 {
599 compatible = "rockchip,rk3288-cru";
600 reg = <0xff760000 0x1000>;
601 rockchip,grf = <&grf>;
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]602 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]603 #clock-cells = <1>;
604 #reset-cells = <1>;
605 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
606 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
607 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
608 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
609 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
610 <&cru PCLK_PERI>;
611 assigned-clock-rates = <0>, <0>,
612 <594000000>, <400000000>,
613 <500000000>, <300000000>,
614 <150000000>, <75000000>,
615 <300000000>, <150000000>,
616 <75000000>;
617 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
618 };
619
620 grf: syscon@ff770000 {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]621 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]622 compatible = "rockchip,rk3288-grf", "syscon";
623 reg = <0xff770000 0x1000>;
624 };
625
626 wdt: watchdog@ff800000 {
627 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
628 reg = <0xff800000 0x100>;
629 clocks = <&cru PCLK_WDT>;
630 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
631 status = "disabled";
632 };
633
634 i2s: i2s@ff890000 {
635 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
636 reg = <0xff890000 0x10000>;
637 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
638 #address-cells = <1>;
639 #size-cells = <0>;
640 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
641 dma-names = "tx", "rx";
642 clock-names = "i2s_hclk", "i2s_clk";
643 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&i2s0_bus>;
646 status = "disabled";
647 };
648
649 vopb: vop@ff930000 {
650 compatible = "rockchip,rk3288-vop";
651 reg = <0xff930000 0x19c>;
652 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
654 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
655 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
656 reset-names = "axi", "ahb", "dclk";
657 iommus = <&vopb_mmu>;
658 power-domains = <&power RK3288_PD_VIO>;
659 status = "disabled";
660 vopb_out: port {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 vopb_out_edp: endpoint@0 {
664 reg = <0>;
665 remote-endpoint = <&edp_in_vopb>;
666 };
667 vopb_out_hdmi: endpoint@1 {
668 reg = <1>;
669 remote-endpoint = <&hdmi_in_vopb>;
670 };
671 };
672 };
673
674 vopb_mmu: iommu@ff930300 {
675 compatible = "rockchip,iommu";
676 reg = <0xff930300 0x100>;
677 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
678 interrupt-names = "vopb_mmu";
679 power-domains = <&power RK3288_PD_VIO>;
680 #iommu-cells = <0>;
681 status = "disabled";
682 };
683
684 vopl: vop@ff940000 {
685 compatible = "rockchip,rk3288-vop";
686 reg = <0xff940000 0x19c>;
687 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
689 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
690 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
691 reset-names = "axi", "ahb", "dclk";
692 iommus = <&vopl_mmu>;
693 power-domains = <&power RK3288_PD_VIO>;
694 status = "disabled";
Simon Glass74336f72016-01-21 19:45:19 -0700[diff] [blame^]695 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]696 vopl_out: port {
697 #address-cells = <1>;
698 #size-cells = <0>;
699 vopl_out_edp: endpoint@0 {
700 reg = <0>;
701 remote-endpoint = <&edp_in_vopl>;
702 };
703 vopl_out_hdmi: endpoint@1 {
704 reg = <1>;
705 remote-endpoint = <&hdmi_in_vopl>;
706 };
707
708 };
709 };
710
711 vopl_mmu: iommu@ff940300 {
712 compatible = "rockchip,iommu";
713 reg = <0xff940300 0x100>;
714 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
715 interrupt-names = "vopl_mmu";
716 power-domains = <&power RK3288_PD_VIO>;
717 #iommu-cells = <0>;
718 status = "disabled";
719 };
720
721 edp: edp@ff970000 {
722 compatible = "rockchip,rk3288-edp";
723 reg = <0xff970000 0x4000>;
724 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
726 rockchip,grf = <&grf>;
727 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
728 resets = <&cru 111>;
729 reset-names = "edp";
730 power-domains = <&power RK3288_PD_VIO>;
731 status = "disabled";
732 ports {
733 edp_in: port {
734 #address-cells = <1>;
735 #size-cells = <0>;
736 edp_in_vopb: endpoint@0 {
737 reg = <0>;
738 remote-endpoint = <&vopb_out_edp>;
739 };
740 edp_in_vopl: endpoint@1 {
741 reg = <1>;
742 remote-endpoint = <&vopl_out_edp>;
743 };
744 };
745 };
746 };
747
748 hdmi: hdmi@ff980000 {
749 compatible = "rockchip,rk3288-dw-hdmi";
750 reg = <0xff980000 0x20000>;
751 reg-io-width = <4>;
752 ddc-i2c-bus = <&i2c5>;
753 rockchip,grf = <&grf>;
754 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
756 clock-names = "iahb", "isfr";
757 status = "disabled";
758 ports {
759 hdmi_in: port {
760 #address-cells = <1>;
761 #size-cells = <0>;
762 hdmi_in_vopb: endpoint@0 {
763 reg = <0>;
764 remote-endpoint = <&vopb_out_hdmi>;
765 };
766 hdmi_in_vopl: endpoint@1 {
767 reg = <1>;
768 remote-endpoint = <&vopl_out_hdmi>;
769 };
770 };
771 };
772 };
773
774 hdmi_audio: hdmi_audio {
775 compatible = "rockchip,rk3288-hdmi-audio";
776 i2s-controller = <&i2s>;
777 status = "disable";
778 };
779
780 vpu: video-codec@ff9a0000 {
781 compatible = "rockchip,rk3288-vpu";
782 reg = <0xff9a0000 0x800>;
783 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
785 interrupt-names = "vepu", "vdpu";
786 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
787 clock-names = "aclk_vcodec", "hclk_vcodec";
788 power-domains = <&power RK3288_PD_VIDEO>;
789 iommus = <&vpu_mmu>;
790 };
791
792 vpu_mmu: iommu@ff9a0800 {
793 compatible = "rockchip,iommu";
794 reg = <0xff9a0800 0x100>;
795 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
796 interrupt-names = "vpu_mmu";
797 power-domains = <&power RK3288_PD_VIDEO>;
798 #iommu-cells = <0>;
799 };
800
801 gpu: gpu@ffa30000 {
802 compatible = "arm,malit764",
803 "arm,malit76x",
804 "arm,malit7xx",
805 "arm,mali-midgard";
806 reg = <0xffa30000 0x10000>;
807 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "JOB", "MMU", "GPU";
811 clocks = <&cru ACLK_GPU>;
812 clock-names = "aclk_gpu";
813 operating-points = <
814 /* KHz uV */
815 100000 950000
816 200000 950000
817 300000 1000000
818 400000 1100000
819 /* 500000 1200000 - See crosbug.com/p/33857 */
820 600000 1250000
821 >;
822 power-domains = <&power RK3288_PD_GPU>;
823 status = "disabled";
824 };
825
826 noc: syscon@ffac0000 {
Simon Glass73a88d02015-08-30 16:55:21 -0600[diff] [blame]827 u-boot,dm-pre-reloc;
Simon Glass344c8372015-08-30 16:55:20 -0600[diff] [blame]828 compatible = "rockchip,rk3288-noc", "syscon";
829 reg = <0xffac0000 0x2000>;
830 };
831
832 efuse: efuse@ffb40000 {
833 compatible = "rockchip,rk3288-efuse";
834 reg = <0xffb40000 0x10000>;
835 status = "disabled";
836 };
837
838 gic: interrupt-controller@ffc01000 {
839 compatible = "arm,gic-400";
840 interrupt-controller;
841 #interrupt-cells = <3>;
842 #address-cells = <0>;
843
844 reg = <0xffc01000 0x1000>,
845 <0xffc02000 0x1000>,
846 <0xffc04000 0x2000>,
847 <0xffc06000 0x2000>;
848 interrupts = <GIC_PPI 9 0xf04>;
849 };
850
851 cpuidle: cpuidle {
852 compatible = "rockchip,rk3288-cpuidle";
853 };
854
855 usbphy: phy {
856 compatible = "rockchip,rk3288-usb-phy";
857 rockchip,grf = <&grf>;
858 #address-cells = <1>;
859 #size-cells = <0>;
860 status = "disabled";
861
862 usbphy0: usb-phy0 {
863 #phy-cells = <0>;
864 reg = <0x320>;
865 clocks = <&cru SCLK_OTGPHY0>;
866 clock-names = "phyclk";
867 };
868
869 usbphy1: usb-phy1 {
870 #phy-cells = <0>;
871 reg = <0x334>;
872 clocks = <&cru SCLK_OTGPHY1>;
873 clock-names = "phyclk";
874 };
875
876 usbphy2: usb-phy2 {
877 #phy-cells = <0>;
878 reg = <0x348>;
879 clocks = <&cru SCLK_OTGPHY2>;
880 clock-names = "phyclk";
881 };
882 };
883
884 pinctrl: pinctrl {
885 compatible = "rockchip,rk3288-pinctrl";
886 rockchip,grf = <&grf>;
887 rockchip,pmu = <&pmu>;
888 #address-cells = <1>;
889 #size-cells = <1>;
890 ranges;
891
892 gpio0: gpio0@ff750000 {
893 compatible = "rockchip,gpio-bank";
894 reg = <0xff750000 0x100>;
895 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&cru PCLK_GPIO0>;
897
898 gpio-controller;
899 #gpio-cells = <2>;
900
901 interrupt-controller;
902 #interrupt-cells = <2>;
903 };
904
905 gpio1: gpio1@ff780000 {
906 compatible = "rockchip,gpio-bank";
907 reg = <0xff780000 0x100>;
908 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&cru PCLK_GPIO1>;
910
911 gpio-controller;
912 #gpio-cells = <2>;
913
914 interrupt-controller;
915 #interrupt-cells = <2>;
916 };
917
918 gpio2: gpio2@ff790000 {
919 compatible = "rockchip,gpio-bank";
920 reg = <0xff790000 0x100>;
921 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&cru PCLK_GPIO2>;
923
924 gpio-controller;
925 #gpio-cells = <2>;
926
927 interrupt-controller;
928 #interrupt-cells = <2>;
929 };
930
931 gpio3: gpio3@ff7a0000 {
932 compatible = "rockchip,gpio-bank";
933 reg = <0xff7a0000 0x100>;
934 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&cru PCLK_GPIO3>;
936
937 gpio-controller;
938 #gpio-cells = <2>;
939
940 interrupt-controller;
941 #interrupt-cells = <2>;
942 };
943
944 gpio4: gpio4@ff7b0000 {
945 compatible = "rockchip,gpio-bank";
946 reg = <0xff7b0000 0x100>;
947 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cru PCLK_GPIO4>;
949
950 gpio-controller;
951 #gpio-cells = <2>;
952
953 interrupt-controller;
954 #interrupt-cells = <2>;
955 };
956
957 gpio5: gpio5@ff7c0000 {
958 compatible = "rockchip,gpio-bank";
959 reg = <0xff7c0000 0x100>;
960 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&cru PCLK_GPIO5>;
962
963 gpio-controller;
964 #gpio-cells = <2>;
965
966 interrupt-controller;
967 #interrupt-cells = <2>;
968 };
969
970 gpio6: gpio6@ff7d0000 {
971 compatible = "rockchip,gpio-bank";
972 reg = <0xff7d0000 0x100>;
973 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&cru PCLK_GPIO6>;
975
976 gpio-controller;
977 #gpio-cells = <2>;
978
979 interrupt-controller;
980 #interrupt-cells = <2>;
981 };
982
983 gpio7: gpio7@ff7e0000 {
984 compatible = "rockchip,gpio-bank";
985 reg = <0xff7e0000 0x100>;
986 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&cru PCLK_GPIO7>;
988
989 gpio-controller;
990 #gpio-cells = <2>;
991
992 interrupt-controller;
993 #interrupt-cells = <2>;
994 };
995
996 gpio8: gpio8@ff7f0000 {
997 compatible = "rockchip,gpio-bank";
998 reg = <0xff7f0000 0x100>;
999 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&cru PCLK_GPIO8>;
1001
1002 gpio-controller;
1003 #gpio-cells = <2>;
1004
1005 interrupt-controller;
1006 #interrupt-cells = <2>;
1007 };
1008
1009 pcfg_pull_up: pcfg-pull-up {
1010 bias-pull-up;
1011 };
1012
1013 pcfg_pull_down: pcfg-pull-down {
1014 bias-pull-down;
1015 };
1016
1017 pcfg_pull_none: pcfg-pull-none {
1018 bias-disable;
1019 };
1020
1021 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1022 bias-disable;
1023 drive-strength = <12>;
1024 };
1025
1026 sleep {
1027 global_pwroff: global-pwroff {
1028 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1029 };
1030
1031 ddrio_pwroff: ddrio-pwroff {
1032 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1033 };
1034
1035 ddr0_retention: ddr0-retention {
1036 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1037 };
1038
1039 ddr1_retention: ddr1-retention {
1040 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1041 };
1042 };
1043
1044 i2c0 {
1045 i2c0_xfer: i2c0-xfer {
1046 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1047 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1048 };
1049 };
1050
1051 i2c1 {
1052 i2c1_xfer: i2c1-xfer {
1053 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1054 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1055 };
1056 };
1057
1058 i2c2 {
1059 i2c2_xfer: i2c2-xfer {
1060 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1061 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1062 };
1063 };
1064
1065 i2c3 {
1066 i2c3_xfer: i2c3-xfer {
1067 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1068 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1069 };
1070 };
1071
1072 i2c4 {
1073 i2c4_xfer: i2c4-xfer {
1074 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1075 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1076 };
1077 };
1078
1079 i2c5 {
1080 i2c5_xfer: i2c5-xfer {
1081 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1082 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1083 };
1084 };
1085
1086 i2s0 {
1087 i2s0_bus: i2s0-bus {
1088 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1089 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1090 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1091 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1092 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1093 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1094 };
1095 };
1096
1097 sdmmc {
1098 sdmmc_clk: sdmmc-clk {
1099 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1100 };
1101
1102 sdmmc_cmd: sdmmc-cmd {
1103 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1104 };
1105
1106 sdmmc_cd: sdmcc-cd {
1107 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1108 };
1109
1110 sdmmc_bus1: sdmmc-bus1 {
1111 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1112 };
1113
1114 sdmmc_bus4: sdmmc-bus4 {
1115 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1116 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1117 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1118 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1119 };
1120 };
1121
1122 sdio0 {
1123 sdio0_bus1: sdio0-bus1 {
1124 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1125 };
1126
1127 sdio0_bus4: sdio0-bus4 {
1128 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1129 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1130 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1131 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1132 };
1133
1134 sdio0_cmd: sdio0-cmd {
1135 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1136 };
1137
1138 sdio0_clk: sdio0-clk {
1139 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1140 };
1141
1142 sdio0_cd: sdio0-cd {
1143 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1144 };
1145
1146 sdio0_wp: sdio0-wp {
1147 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1148 };
1149
1150 sdio0_pwr: sdio0-pwr {
1151 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1152 };
1153
1154 sdio0_bkpwr: sdio0-bkpwr {
1155 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1156 };
1157
1158 sdio0_int: sdio0-int {
1159 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1160 };
1161 };
1162
1163 sdio1 {
1164 sdio1_bus1: sdio1-bus1 {
1165 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1166 };
1167
1168 sdio1_bus4: sdio1-bus4 {
1169 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1170 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1171 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1172 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1173 };
1174
1175 sdio1_cd: sdio1-cd {
1176 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1177 };
1178
1179 sdio1_wp: sdio1-wp {
1180 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1181 };
1182
1183 sdio1_bkpwr: sdio1-bkpwr {
1184 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1185 };
1186
1187 sdio1_int: sdio1-int {
1188 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1189 };
1190
1191 sdio1_cmd: sdio1-cmd {
1192 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1193 };
1194
1195 sdio1_clk: sdio1-clk {
1196 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1197 };
1198
1199 sdio1_pwr: sdio1-pwr {
1200 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1201 };
1202 };
1203
1204 emmc {
1205 emmc_clk: emmc-clk {
1206 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1207 };
1208
1209 emmc_cmd: emmc-cmd {
1210 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1211 };
1212
1213 emmc_pwr: emmc-pwr {
1214 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1215 };
1216
1217 emmc_bus1: emmc-bus1 {
1218 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1219 };
1220
1221 emmc_bus4: emmc-bus4 {
1222 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1223 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1224 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1225 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1226 };
1227
1228 emmc_bus8: emmc-bus8 {
1229 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1230 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1231 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1232 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1233 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1234 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1235 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1236 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1237 };
1238 };
1239
1240 spi0 {
1241 spi0_clk: spi0-clk {
1242 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1243 };
1244 spi0_cs0: spi0-cs0 {
1245 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1246 };
1247 spi0_tx: spi0-tx {
1248 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1249 };
1250 spi0_rx: spi0-rx {
1251 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1252 };
1253 spi0_cs1: spi0-cs1 {
1254 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1255 };
1256 };
1257 spi1 {
1258 spi1_clk: spi1-clk {
1259 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1260 };
1261 spi1_cs0: spi1-cs0 {
1262 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1263 };
1264 spi1_rx: spi1-rx {
1265 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1266 };
1267 spi1_tx: spi1-tx {
1268 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1269 };
1270 };
1271
1272 spi2 {
1273 spi2_cs1: spi2-cs1 {
1274 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1275 };
1276 spi2_clk: spi2-clk {
1277 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1278 };
1279 spi2_cs0: spi2-cs0 {
1280 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1281 };
1282 spi2_rx: spi2-rx {
1283 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1284 };
1285 spi2_tx: spi2-tx {
1286 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1287 };
1288 };
1289
1290 uart0 {
1291 uart0_xfer: uart0-xfer {
1292 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1293 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1294 };
1295
1296 uart0_cts: uart0-cts {
1297 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1298 };
1299
1300 uart0_rts: uart0-rts {
1301 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1302 };
1303 };
1304
1305 uart1 {
1306 uart1_xfer: uart1-xfer {
1307 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1308 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1309 };
1310
1311 uart1_cts: uart1-cts {
1312 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1313 };
1314
1315 uart1_rts: uart1-rts {
1316 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1317 };
1318 };
1319
1320 uart2 {
1321 uart2_xfer: uart2-xfer {
1322 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1323 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1324 };
1325 /* no rts / cts for uart2 */
1326 };
1327
1328 uart3 {
1329 uart3_xfer: uart3-xfer {
1330 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1331 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1332 };
1333
1334 uart3_cts: uart3-cts {
1335 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1336 };
1337
1338 uart3_rts: uart3-rts {
1339 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1340 };
1341 };
1342
1343 uart4 {
1344 uart4_xfer: uart4-xfer {
1345 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1346 <5 13 3 &pcfg_pull_none>;
1347 };
1348
1349 uart4_cts: uart4-cts {
1350 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1351 };
1352
1353 uart4_rts: uart4-rts {
1354 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1355 };
1356 };
1357
1358 tsadc {
1359 otp_out: otp-out {
1360 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1361 };
1362 };
1363
1364 pwm0 {
1365 pwm0_pin: pwm0-pin {
1366 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1367 };
1368 };
1369
1370 pwm1 {
1371 pwm1_pin: pwm1-pin {
1372 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1373 };
1374 };
1375
1376 pwm2 {
1377 pwm2_pin: pwm2-pin {
1378 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1379 };
1380 };
1381
1382 pwm3 {
1383 pwm3_pin: pwm3-pin {
1384 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1385 };
1386 };
1387
1388 gmac {
1389 rgmii_pins: rgmii-pins {
1390 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1391 <3 31 3 &pcfg_pull_none>,
1392 <3 26 3 &pcfg_pull_none>,
1393 <3 27 3 &pcfg_pull_none>,
1394 <3 28 3 &pcfg_pull_none_12ma>,
1395 <3 29 3 &pcfg_pull_none_12ma>,
1396 <3 24 3 &pcfg_pull_none_12ma>,
1397 <3 25 3 &pcfg_pull_none_12ma>,
1398 <4 0 3 &pcfg_pull_none>,
1399 <4 5 3 &pcfg_pull_none>,
1400 <4 6 3 &pcfg_pull_none>,
1401 <4 9 3 &pcfg_pull_none_12ma>,
1402 <4 4 3 &pcfg_pull_none_12ma>,
1403 <4 1 3 &pcfg_pull_none>,
1404 <4 3 3 &pcfg_pull_none>;
1405 };
1406
1407 rmii_pins: rmii-pins {
1408 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1409 <3 31 3 &pcfg_pull_none>,
1410 <3 28 3 &pcfg_pull_none>,
1411 <3 29 3 &pcfg_pull_none>,
1412 <4 0 3 &pcfg_pull_none>,
1413 <4 5 3 &pcfg_pull_none>,
1414 <4 4 3 &pcfg_pull_none>,
1415 <4 1 3 &pcfg_pull_none>,
1416 <4 2 3 &pcfg_pull_none>,
1417 <4 3 3 &pcfg_pull_none>;
1418 };
1419 };
1420 };
1421
1422 power: power-controller {
1423 compatible = "rockchip,rk3288-power-controller";
1424 #power-domain-cells = <1>;
1425 rockchip,pmu = <&pmu>;
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428
1429 pd_gpu {
1430 reg = <RK3288_PD_GPU>;
1431 clocks = <&cru ACLK_GPU>;
1432 };
1433
1434 pd_hevc {
1435 reg = <RK3288_PD_HEVC>;
1436 clocks = <&cru ACLK_HEVC>,
1437 <&cru SCLK_HEVC_CABAC>,
1438 <&cru SCLK_HEVC_CORE>,
1439 <&cru HCLK_HEVC>;
1440 };
1441
1442 pd_vio {
1443 reg = <RK3288_PD_VIO>;
1444 clocks = <&cru ACLK_IEP>,
1445 <&cru ACLK_ISP>,
1446 <&cru ACLK_RGA>,
1447 <&cru ACLK_VIP>,
1448 <&cru ACLK_VOP0>,
1449 <&cru ACLK_VOP1>,
1450 <&cru DCLK_VOP0>,
1451 <&cru DCLK_VOP1>,
1452 <&cru HCLK_IEP>,
1453 <&cru HCLK_ISP>,
1454 <&cru HCLK_RGA>,
1455 <&cru HCLK_VIP>,
1456 <&cru HCLK_VOP0>,
1457 <&cru HCLK_VOP1>,
1458 <&cru PCLK_EDP_CTRL>,
1459 <&cru PCLK_HDMI_CTRL>,
1460 <&cru PCLK_LVDS_PHY>,
1461 <&cru PCLK_MIPI_CSI>,
1462 <&cru PCLK_MIPI_DSI0>,
1463 <&cru PCLK_MIPI_DSI1>,
1464 <&cru SCLK_EDP_24M>,
1465 <&cru SCLK_EDP>,
1466 <&cru SCLK_HDMI_CEC>,
1467 <&cru SCLK_HDMI_HDCP>,
1468 <&cru SCLK_ISP_JPE>,
1469 <&cru SCLK_ISP>,
1470 <&cru SCLK_RGA>;
1471 };
1472
1473 pd_video {
1474 reg = <RK3288_PD_VIDEO>;
1475 clocks = <&cru ACLK_VCODEC>,
1476 <&cru HCLK_VCODEC>;
1477 };
1478 };
1479};