blob: ca40e4e0bce6a90e37de1c622790032a8721d07d [file] [log] [blame]
Tom Warren74652cf2011-04-14 12:18:06 +00001/*
2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warren74652cf2011-04-14 12:18:06 +00006 */
7#include <asm/types.h>
8
9/* Stabilization delays, in usec */
Tom Warrenb2871032012-12-11 13:34:15 +000010#define PLL_STABILIZATION_DELAY (300)
Tom Warren74652cf2011-04-14 12:18:06 +000011#define IO_STABILIZATION_DELAY (1000)
12
Tom Warren74652cf2011-04-14 12:18:06 +000013#define PLLX_ENABLED (1 << 30)
14#define CCLK_BURST_POLICY 0x20008888
15#define SUPER_CCLK_DIVIDER 0x80000000
16
17/* Calculate clock fractional divider value from ref and target frequencies */
Tom Warrenb2871032012-12-11 13:34:15 +000018#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
Tom Warren74652cf2011-04-14 12:18:06 +000019
20/* Calculate clock frequency value from reference and clock divider value */
Tom Warrenb2871032012-12-11 13:34:15 +000021#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
Tom Warren74652cf2011-04-14 12:18:06 +000022
23/* AVP/CPU ID */
24#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
Tom Warrenb2871032012-12-11 13:34:15 +000025#define PG_UP_TAG_0 0x0
Tom Warren74652cf2011-04-14 12:18:06 +000026
27#define CORESIGHT_UNLOCK 0xC5ACCE55;
28
Tom Warrenb2871032012-12-11 13:34:15 +000029/* AP base physical address of internal SRAM */
30#define NV_PA_BASE_SRAM 0x40000000
Tom Warren74652cf2011-04-14 12:18:06 +000031
32#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
33#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
34#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
35
36#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
37#define FLOW_MODE_STOP 2
38#define HALT_COP_EVENT_JTAG (1 << 28)
39#define HALT_COP_EVENT_IRQ_1 (1 << 11)
40#define HALT_COP_EVENT_FIQ_1 (1 << 9)
41
Simon Glass210576f2011-11-05 03:56:50 +000042/* This is the main entry into U-Boot, used by the Cortex-A9 */
43extern void _start(void);
Simon Glassd5153622012-04-02 13:18:50 +000044
45/**
Tom Warren49493cb2013-04-10 10:32:32 -070046 * Works out the SOC/SKU type used for clocks settings
Simon Glassd5153622012-04-02 13:18:50 +000047 *
48 * @return SOC type - see TEGRA_SOC...
49 */
Tom Warren49493cb2013-04-10 10:32:32 -070050int tegra_get_chip_sku(void);
51
52/**
53 * Returns the pure SOC (chip ID) from the HIDREV register
54 *
55 * @return SOC ID - see CHIPID_TEGRAxx...
56 */
57int tegra_get_chip(void);
58
59/**
60 * Returns the SKU ID from the sku_info register
61 *
62 * @return SKU ID - see SKU_ID_Txx...
63 */
64int tegra_get_sku_info(void);
65
66/* Do any chip-specific cache config */
Tom Warrend0edce42013-03-25 16:22:26 -070067void config_cache(void);
Bryan Wudf3443d2014-06-24 11:45:29 +090068
69#if defined(CONFIG_TEGRA124)
70/* Do chip-specific vpr config */
71void config_vpr(void);
72#else
73static inline void config_vpr(void)
74{
75}
76#endif
Stephen Warren73c38932015-01-19 16:25:52 -070077
78#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
79bool tegra_cpu_is_non_secure(void);
80#endif