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Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05301/*
2 * Xilinx ZC770 XM012 board DTS
3 *
Michal Simek5c45b162015-07-22 11:36:32 +02004 * Copyright (C) 2013 - 2015 Xilinx, Inc.
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05305 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053012 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
Michal Simek5c45b162015-07-22 11:36:32 +020013 model = "Xilinx Zynq";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090014
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090015 aliases {
Michal Simek5c45b162015-07-22 11:36:32 +020016 i2c0 = &i2c0;
17 i2c1 = &i2c1;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090018 serial0 = &uart1;
Michal Simek5c45b162015-07-22 11:36:32 +020019 spi0 = &spi1;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090020 };
21
Michal Simek5c45b162015-07-22 11:36:32 +020022 chosen {
23 bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
24 linux,stdout-path = &uart1;
25 stdout-path = &uart1;
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090026 };
Michal Simek5c45b162015-07-22 11:36:32 +020027
28 memory@0 {
29 device_type = "memory";
30 reg = <0x0 0x40000000>;
31 };
32};
33
34&spi1 {
35 status = "okay";
36 num-cs = <4>;
37 is-decoded-cs = <0>;
38};
39
40&can1 {
41 status = "okay";
42};
43
44&i2c0 {
45 status = "okay";
46 clock-frequency = <400000>;
47
48 m24c02_eeprom@52 {
49 compatible = "at,24c02";
50 reg = <0x52>;
51 };
52};
53
54&i2c1 {
55 status = "okay";
56 clock-frequency = <400000>;
57
58 m24c02_eeprom@52 {
59 compatible = "at,24c02";
60 reg = <0x52>;
61 };
62};
63
64&uart1 {
65 status = "okay";
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053066};