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wdenk8966f332002-10-31 23:30:59 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * (C) Copyright 2001
5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
6 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 * [derived from config_TQM850L.h]
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*
36 * High Level Configuration Options
37 * (easy to change)
38 */
39
40#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
41#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
42
43/*
44 * Port assignments (CONFIG_LANTEC == 1):
45 * - SMC1: J11 (MDB) ?
46 * - SMC2: J6 (Feature connector)
47 * - SCC2: J9 (RJ45)
48 * - SCC3: J8 (Sub-D9)
49 *
50 * Port assignments (CONFIG_LANTEC == 2): TBD
51 */
52
53
54#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
55#define CONFIG_8xx_CONS_SCC3
56#undef CONFIG_8xx_CONS_NONE
57#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
58#if 0
59#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60#else
61#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
62#endif
63
64#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
65
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
69
70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
71#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
72
73#undef CONFIG_WATCHDOG /* watchdog disabled */
74
75#define CONFIG_STATUS_LED 1 /* Status LED enabled */
76
77#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
78
79#define CONFIG_CMD_MINIMAL 0
80#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \
81 CFG_CMD_MEMORY | \
82 CFG_CMD_LOADS | \
83 CFG_CMD_LOADB)
84#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD)
85#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
86#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
wdenk824a1eb2003-04-20 16:49:37 +000087 & ~CFG_CMD_BMP \
wdenk8966f332002-10-31 23:30:59 +000088 & ~CFG_CMD_BSP \
89 & ~CFG_CMD_DOC \
90 & ~CFG_CMD_DTT \
91 & ~CFG_CMD_EEPROM \
92 & ~CFG_CMD_ELF \
93 & ~CFG_CMD_FDC \
wdenk2262cfe2002-11-18 00:14:45 +000094 & ~CFG_CMD_FDOS \
wdenk8966f332002-10-31 23:30:59 +000095 & ~CFG_CMD_HWFLOW \
96 & ~CFG_CMD_I2C \
97 & ~CFG_CMD_IDE \
98 & ~CFG_CMD_IRQ \
99 & ~CFG_CMD_JFFS2 \
100 & ~CFG_CMD_KGDB \
101 & ~CFG_CMD_MII \
wdenk71f95112003-06-15 22:40:42 +0000102 & ~CFG_CMD_MMC \
wdenkac6dbb82003-03-26 11:42:53 +0000103 & ~CFG_CMD_NAND \
wdenk8966f332002-10-31 23:30:59 +0000104 & ~CFG_CMD_PCI \
105 & ~CFG_CMD_PCMCIA \
106 & ~CFG_CMD_SCSI \
wdenk1d0350e2002-11-11 21:14:20 +0000107 & ~CFG_CMD_SPI \
wdenk8966f332002-10-31 23:30:59 +0000108 & ~CFG_CMD_USB \
109 & ~CFG_CMD_VFD )
110
111#if CONFIG_LANTEC >= 2
112#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
113#endif
114
115#if CONFIG_LANTEC >= 2
116# define CONFIG_COMMANDS CONFIG_CMD_FULL
117#else
118# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET)
119#endif
120
121/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
122#include <cmd_confdefs.h>
123
124/*
125 * Miscellaneous configurable options
126 */
127#define CFG_LONGHELP /* undef to save memory */
128#define CFG_PROMPT "=> " /* Monitor Command Prompt */
129#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
130#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
131#else
132#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
133#endif
134#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
135#define CFG_MAXARGS 16 /* max number of command args */
136#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
137
138#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
139#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
140
141#define CFG_LOAD_ADDR 0x100000 /* default load address */
142
143#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
144
145#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
146
147/*
148 * Low Level Configuration Settings
149 * (address mappings, register initial values, etc.)
150 * You should know what you are doing if you make changes here.
151 */
152/*-----------------------------------------------------------------------
153 * Internal Memory Mapped Register
154 */
155#define CFG_IMMR 0xFFF00000
156
157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
160#define CFG_INIT_RAM_ADDR CFG_IMMR
161#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
162#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
163#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
164#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165
166/*-----------------------------------------------------------------------
167 * Start addresses for the final memory configuration
168 * (Set up by the startup code)
169 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 */
171#define CFG_SDRAM_BASE 0x00000000
172#define CFG_FLASH_BASE 0x40000000
173#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
174#define CFG_MONITOR_BASE CFG_FLASH_BASE
175#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
176
177/*
178 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization.
181 */
182#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
183
184/*-----------------------------------------------------------------------
185 * FLASH organization
186 */
187#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
188#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
189
190#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
191#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
192
193#define CFG_ENV_IS_IN_FLASH 1
194#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
195#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
196
197/*-----------------------------------------------------------------------
198 * Cache Configuration
199 */
200#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
201#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
202#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
203#endif
204
205/*-----------------------------------------------------------------------
206 * SYPCR - System Protection Control 11-9
207 * SYPCR can only be written once after reset!
208 *-----------------------------------------------------------------------
209 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
210 */
211#if defined(CONFIG_WATCHDOG)
212#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
213 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
214#else
215#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
216#endif
217
218/*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration 11-6
220 *-----------------------------------------------------------------------
221 * PCMCIA config., multi-function pin tri-state
222 */
223#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
224
225/*-----------------------------------------------------------------------
226 * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
227 *-----------------------------------------------------------------------
228 */
229#define CONFIG_8xx_GCLK_FREQ 33000000
230
231/*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
235 */
236#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
237
238/*-----------------------------------------------------------------------
239 * RTCSC - Real-Time Clock Status and Control Register 11-27
240 *-----------------------------------------------------------------------
241 */
242#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
243
244/*-----------------------------------------------------------------------
245 * PISCR - Periodic Interrupt Status and Control 11-31
246 *-----------------------------------------------------------------------
247 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
248 */
249#define CFG_PISCR (PISCR_PS | PISCR_PITF)
250
251/*-----------------------------------------------------------------------
252 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
253 *-----------------------------------------------------------------------
254 * Reset PLL lock status sticky bit, timer expired status bit and timer
255 * interrupt status bit
256 *
257 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
258 */
259 /* up to 50 MHz we use a 1:1 clock */
260#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
261
262/*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
267 */
268#define SCCR_MASK SCCR_EBDF11
269 /* up to 50 MHz we use a 1:1 clock */
270#define CFG_SCCR (SCCR_TBS | \
271 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
272 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
273 SCCR_DFALCD00)
274
275/*-----------------------------------------------------------------------
276 *
277 *-----------------------------------------------------------------------
278 *
279 */
wdenk8966f332002-10-31 23:30:59 +0000280#define CFG_DER 0
281
282/*
283 * Init Memory Controller:
284 *
285 * BR0/5 and OR0/5 (FLASH)
286 */
287
288#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
289#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */
290
291/* used to re-map FLASH both when starting from SRAM or FLASH:
292 * restrict access enough to keep SRAM working (if any)
293 * but not too much to meddle with FLASH accesses
294 */
295#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
296#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
297
298/* FLASH timing */
299#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
300 OR_SCY_5_CLK | OR_TRLX)
301
302#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
303#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
304#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
305
306#define CFG_OR5_REMAP CFG_OR0_REMAP
307#define CFG_OR5_PRELIM CFG_OR0_PRELIM
308#define CFG_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
309
310/*
311 * BR2/3 and OR2/3 (SDRAM)
312 *
313 */
314#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
315#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
316
317/* SDRAM timing: Multiplexed addresses */
318#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM)
319
320#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
321#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
322
323/*
324 * Memory Periodic Timer Prescaler
325 */
326
327/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
328#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
329#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
330
331/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
332#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
333#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
334
335/*
336 * MAMR settings for SDRAM
337 */
338/* periodic timer for refresh */
339#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
340
341/* 8 column SDRAM */
342#define CFG_MAMR_8COL \
343 ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
344 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
345 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
346
347/*
348 * Internal Definitions
349 *
350 * Boot Flags
351 */
352#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
353#define BOOTFLAG_WARM 0x02 /* Software reboot */
354
355#endif /* __CONFIG_H */