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gerrit.cesnet.cz / github / trini / u-boot / 71edc271816ec82cf0550dd6980be2da3cc2ad9e / . / include / asm-m68k / m5275.h
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Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]1/*
2 * MCF5275 Internal Memory Map
3 *
4 * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
5 * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __M5275_H__
27#define __M5275_H__
28
29/*
30 * Define the 5275 SIM register set addresses. These are similar,
31 * but not quite identical to the 5282 registers and offsets.
32 */
33#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
34#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
35#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
36#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
37#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
38#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
39#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
40#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
41#define MCFINTC_IRLR 0x18 /* */
42#define MCFINTC_IACKL 0x19 /* */
43#define MCFINTC_ICR0 0x40 /* Base ICR register */
44
45#define MCF_GPIO_PAR_UART 0x10007c
46#define UART0_ENABLE_MASK 0x000f
47#define UART1_ENABLE_MASK 0x00f0
48#define UART2_ENABLE_MASK 0x3f00
49
50#define MCF_GPIO_PAR_FECI2C 0x100082
51#define PAR_SDA_ENABLE_MASK 0x0003
52#define PAR_SCL_ENABLE_MASK 0x000c
53
54#define MCFSIM_WRRR 0x140000
55#define MCFSIM_SDCR 0x40
56
57/*********************************************************************
58 * SDRAM Controller (SDRAMC)
59 *********************************************************************/
60
61/* Register read/write macros */
62#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
63#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
64#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
65#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
66#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
67#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
68#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
69#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
70
71/* Bit definitions and macros for MCF_SDRAMC_SDMR */
72#define MCF_SDRAMC_SDMR_CMD (0x00010000)
73#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
74#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
75#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
76#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
77
78/* Bit definitions and macros for MCF_SDRAMC_SDCR */
79#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
80#define MCF_SDRAMC_SDCR_IREF (0x00000004)
81#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
82#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
83#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
84#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
85#define MCF_SDRAMC_SDCR_REF (0x10000000)
86#define MCF_SDRAMC_SDCR_CKE (0x40000000)
87#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
88
89/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
90#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
91#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
92#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
93#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
94#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
95#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
96#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
97
98/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
99#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
100#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
101#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
102#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
103
104/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
105#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
106#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
107
108/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
109#define MCF_SDRAMC_SDMRn_V (0x00000001)
110#define MCF_SDRAMC_SDMRn_WP (0x00000080)
111#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
112#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
113#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
114#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
115#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
116#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
117#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
118#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
119#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
120#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
121#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
122#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
123#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
124#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
125#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
126#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
127#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
128#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
129#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
130#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
131
132/*********************************************************************
133 * Interrupt Controller (INTC)
134 ********************************************************************/
135#define INT0_LO_RSVD0 (0)
136#define INT0_LO_EPORT1 (1)
137#define INT0_LO_EPORT2 (2)
138#define INT0_LO_EPORT3 (3)
139#define INT0_LO_EPORT4 (4)
140#define INT0_LO_EPORT5 (5)
141#define INT0_LO_EPORT6 (6)
142#define INT0_LO_EPORT7 (7)
143#define INT0_LO_SCM (8)
144#define INT0_LO_DMA0 (9)
145#define INT0_LO_DMA1 (10)
146#define INT0_LO_DMA2 (11)
147#define INT0_LO_DMA3 (12)
148#define INT0_LO_UART0 (13)
149#define INT0_LO_UART1 (14)
150#define INT0_LO_UART2 (15)
151#define INT0_LO_RSVD1 (16)
152#define INT0_LO_I2C (17)
153#define INT0_LO_QSPI (18)
154#define INT0_LO_DTMR0 (19)
155#define INT0_LO_DTMR1 (20)
156#define INT0_LO_DTMR2 (21)
157#define INT0_LO_DTMR3 (22)
158#define INT0_LO_FEC0_TXF (23)
159#define INT0_LO_FEC0_TXB (24)
160#define INT0_LO_FEC0_UN (25)
161#define INT0_LO_FEC0_RL (26)
162#define INT0_LO_FEC0_RXF (27)
163#define INT0_LO_FEC0_RXB (28)
164#define INT0_LO_FEC0_MII (29)
165#define INT0_LO_FEC0_LC (30)
166#define INT0_LO_FEC0_HBERR (31)
167#define INT0_HI_FEC0_GRA (32)
168#define INT0_HI_FEC0_EBERR (33)
169#define INT0_HI_FEC0_BABT (34)
170#define INT0_HI_FEC0_BABR (35)
171#define INT0_HI_PIT0 (36)
172#define INT0_HI_PIT1 (37)
173#define INT0_HI_PIT2 (38)
174#define INT0_HI_PIT3 (39)
175#define INT0_HI_RNG (40)
176#define INT0_HI_SKHA (41)
177#define INT0_HI_MDHA (42)
178#define INT0_HI_USB (43)
179#define INT0_HI_USB_EP0 (44)
180#define INT0_HI_USB_EP1 (45)
181#define INT0_HI_USB_EP2 (46)
182#define INT0_HI_USB_EP3 (47)
183/* 48-63 Reserved */
184
185/* 0-22 Reserved */
186#define INT1_LO_FEC1_TXF (23)
187#define INT1_LO_FEC1_TXB (24)
188#define INT1_LO_FEC1_UN (25)
189#define INT1_LO_FEC1_RL (26)
190#define INT1_LO_FEC1_RXF (27)
191#define INT1_LO_FEC1_RXB (28)
192#define INT1_LO_FEC1_MII (29)
193#define INT1_LO_FEC1_LC (30)
194#define INT1_LO_FEC1_HBERR (31)
195#define INT1_HI_FEC1_GRA (32)
196#define INT1_HI_FEC1_EBERR (33)
197#define INT1_HI_FEC1_BABT (34)
198#define INT1_HI_FEC1_BABR (35)
199/* 36-63 Reserved */
200
201/* Bit definitions and macros for INTC_IPRL */
202#define INTC_IPRL_INT31 (0x80000000)
203#define INTC_IPRL_INT30 (0x40000000)
204#define INTC_IPRL_INT29 (0x20000000)
205#define INTC_IPRL_INT28 (0x10000000)
206#define INTC_IPRL_INT27 (0x08000000)
207#define INTC_IPRL_INT26 (0x04000000)
208#define INTC_IPRL_INT25 (0x02000000)
209#define INTC_IPRL_INT24 (0x01000000)
210#define INTC_IPRL_INT23 (0x00800000)
211#define INTC_IPRL_INT22 (0x00400000)
212#define INTC_IPRL_INT21 (0x00200000)
213#define INTC_IPRL_INT20 (0x00100000)
214#define INTC_IPRL_INT19 (0x00080000)
215#define INTC_IPRL_INT18 (0x00040000)
216#define INTC_IPRL_INT17 (0x00020000)
217#define INTC_IPRL_INT16 (0x00010000)
218#define INTC_IPRL_INT15 (0x00008000)
219#define INTC_IPRL_INT14 (0x00004000)
220#define INTC_IPRL_INT13 (0x00002000)
221#define INTC_IPRL_INT12 (0x00001000)
222#define INTC_IPRL_INT11 (0x00000800)
223#define INTC_IPRL_INT10 (0x00000400)
224#define INTC_IPRL_INT9 (0x00000200)
225#define INTC_IPRL_INT8 (0x00000100)
226#define INTC_IPRL_INT7 (0x00000080)
227#define INTC_IPRL_INT6 (0x00000040)
228#define INTC_IPRL_INT5 (0x00000020)
229#define INTC_IPRL_INT4 (0x00000010)
230#define INTC_IPRL_INT3 (0x00000008)
231#define INTC_IPRL_INT2 (0x00000004)
232#define INTC_IPRL_INT1 (0x00000002)
233#define INTC_IPRL_INT0 (0x00000001)
234
235/* Bit definitions and macros for RCR */
236#define RCM_RCR_FRCRSTOUT (0x40)
237#define RCM_RCR_SOFTRST (0x80)
238
239#define FMPLL_SYNSR_LOCK (0x00000008)
240
241#endif /* __M5275_H__ */