| TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * MCF5253 Internal Memory Map |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __IMMAP_5249__ |
| 27 | #define __IMMAP_5249__ |
| 28 | |
| 29 | #define MMAP_INTC (CFG_MBAR + 0x00000040) |
| 30 | #define MMAP_DTMR0 (CFG_MBAR + 0x00000140) |
| 31 | #define MMAP_DTMR1 (CFG_MBAR + 0x00000180) |
| 32 | #define MMAP_UART0 (CFG_MBAR + 0x000001C0) |
| 33 | #define MMAP_UART1 (CFG_MBAR + 0x00000200) |
| 34 | #define MMAP_I2C0 (CFG_MBAR + 0x00000280) |
| 35 | #define MMAP_QSPI (CFG_MBAR + 0x00000400) |
| 36 | #define MMAP_CAN0 (CFG_MBAR + 0x00010000) |
| 37 | #define MMAP_CAN1 (CFG_MBAR + 0x00011000) |
| 38 | |
| 39 | #define MMAP_I2C1 (CFG_MBAR2 + 0x00000440) |
| 40 | #define MMAP_UART2 (CFG_MBAR2 + 0x00000C00) |
| 41 | |
| 42 | /********************************************************************* |
| 43 | * ATA Module (ATAC) |
| 44 | *********************************************************************/ |
| 45 | |
| 46 | /* Register read/write struct */ |
| 47 | typedef struct atac { |
| 48 | /* PIO */ |
| 49 | u8 toff; /* 0x00 */ |
| 50 | u8 ton; /* 0x01 */ |
| 51 | u8 t1; /* 0x02 */ |
| 52 | u8 t2w; /* 0x03 */ |
| 53 | u8 t2r; /* 0x04 */ |
| 54 | u8 ta; /* 0x05 */ |
| 55 | u8 trd; /* 0x06 */ |
| 56 | u8 t4; /* 0x07 */ |
| 57 | u8 t9; /* 0x08 */ |
| 58 | |
| 59 | /* DMA */ |
| 60 | u8 tm; /* 0x09 */ |
| 61 | u8 tn; /* 0x0A */ |
| 62 | u8 td; /* 0x0B */ |
| 63 | u8 tk; /* 0x0C */ |
| 64 | u8 tack; /* 0x0D */ |
| 65 | u8 tenv; /* 0x0E */ |
| 66 | u8 trp; /* 0x0F */ |
| 67 | u8 tzah; /* 0x10 */ |
| 68 | u8 tmli; /* 0x11 */ |
| 69 | u8 tdvh; /* 0x12 */ |
| 70 | u8 tdzfs; /* 0x13 */ |
| 71 | u8 tdvs; /* 0x14 */ |
| 72 | u8 tcvh; /* 0x15 */ |
| 73 | u8 tss; /* 0x16 */ |
| 74 | u8 tcyc; /* 0x17 */ |
| 75 | |
| 76 | /* FIFO */ |
| 77 | u32 fifo32; /* 0x18 */ |
| 78 | u16 fifo16; /* 0x1C */ |
| 79 | u8 rsvd0[2]; |
| 80 | u8 ffill; /* 0x20 */ |
| 81 | u8 rsvd1[3]; |
| 82 | |
| 83 | /* ATA */ |
| 84 | u8 cr; /* 0x24 */ |
| 85 | u8 rsvd2[3]; |
| 86 | u8 isr; /* 0x28 */ |
| 87 | u8 rsvd3[3]; |
| 88 | u8 ier; /* 0x2C */ |
| 89 | u8 rsvd4[3]; |
| 90 | u8 icr; /* 0x30 */ |
| 91 | u8 rsvd5[3]; |
| 92 | u8 falarm; /* 0x34 */ |
| 93 | } atac_t; |
| 94 | |
| 95 | #endif /* __IMMAP_5249__ */ |