wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 1 | #include <common.h> |
| 2 | #include <mpc8xx.h> |
| 3 | #include <commproc.h> |
| 4 | |
| 5 | #include "atm.h" |
| 6 | #include <linux/stddef.h> |
| 7 | |
| 8 | #define SYNC __asm__("sync") |
Wolfgang Denk | a566466 | 2008-07-03 23:06:36 +0200 | [diff] [blame] | 9 | #define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 10 | |
| 11 | #define FALSE 1 |
| 12 | #define TRUE 0 |
| 13 | #define OK 0 |
| 14 | #define ERROR -1 |
| 15 | |
| 16 | struct atm_connection_t g_conn[NUM_CONNECTIONS] = |
| 17 | { |
| 18 | { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */ |
| 19 | }; |
| 20 | |
| 21 | struct atm_driver_t g_atm = |
| 22 | { |
| 23 | FALSE, /* loaded */ |
| 24 | FALSE, /* started */ |
| 25 | NULL, /* csram */ |
| 26 | 0, /* csram_size */ |
| 27 | NULL, /* am_top */ |
| 28 | NULL, /* ap_top */ |
| 29 | NULL, /* int_reload_ptr */ |
| 30 | NULL, /* int_serv_ptr */ |
| 31 | NULL, /* rbd_base_ptr */ |
| 32 | NULL, /* tbd_base_ptr */ |
| 33 | 0 /* linerate */ |
| 34 | }; |
| 35 | |
| 36 | char csram[1024]; /* more than enough for doing nothing*/ |
| 37 | |
| 38 | int atmLoad(void); |
| 39 | void atmUnload(void); |
| 40 | int atmMemInit(void); |
| 41 | void atmIntInit(void); |
| 42 | void atmApcInit(void); |
| 43 | void atmAmtInit(void); |
| 44 | void atmCpmInit(void); |
| 45 | void atmUtpInit(void); |
| 46 | |
| 47 | /***************************************************************************** |
| 48 | * |
| 49 | * FUNCTION NAME: atmLoad |
| 50 | * |
| 51 | * DESCRIPTION: Basic ATM initialization. |
| 52 | * |
| 53 | * PARAMETERS: none |
| 54 | * |
| 55 | * RETURNS: OK or ERROR |
| 56 | * |
| 57 | ****************************************************************************/ |
| 58 | int atmLoad() |
| 59 | { |
| 60 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 61 | volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; |
| 62 | volatile iop8xx_t *iop = &immap->im_ioport; |
| 63 | |
| 64 | timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ |
| 65 | immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ |
| 66 | iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ |
| 67 | |
| 68 | if ( atmMemInit() != OK ) return ERROR; |
| 69 | |
| 70 | atmIntInit(); |
| 71 | atmApcInit(); |
| 72 | atmAmtInit(); |
| 73 | atmCpmInit(); |
| 74 | atmUtpInit(); |
| 75 | |
| 76 | g_atm.loaded = TRUE; |
| 77 | |
| 78 | return OK; |
| 79 | } |
| 80 | |
| 81 | /***************************************************************************** |
| 82 | * |
| 83 | * FUNCTION NAME: atmUnload |
| 84 | * |
| 85 | * DESCRIPTION: Disables ATM and UTOPIA. |
| 86 | * |
| 87 | * PARAMETERS: none |
| 88 | * |
| 89 | * RETURNS: void |
| 90 | * |
| 91 | ****************************************************************************/ |
| 92 | void atmUnload() |
| 93 | { |
| 94 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 95 | volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; |
| 96 | volatile iop8xx_t *iop = &immap->im_ioport; |
| 97 | |
| 98 | timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ |
| 99 | immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ |
| 100 | iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ |
| 101 | g_atm.loaded = FALSE; |
| 102 | } |
| 103 | |
| 104 | /***************************************************************************** |
| 105 | * |
| 106 | * FUNCTION NAME: atmMemInit |
| 107 | * |
| 108 | * DESCRIPTION: |
| 109 | * |
| 110 | * The ATM driver uses the following resources: |
| 111 | * |
| 112 | * A. Memory in DPRAM to hold |
| 113 | * |
| 114 | * 1/ CT = Connection Table ( RCT & TCT ) |
| 115 | * 2/ TCTE = Transmit Connection Table Extension |
| 116 | * 3/ MPHYPT = Multi-PHY Pointing Table |
| 117 | * 4/ APCP = APC Parameter Table |
| 118 | * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 ) |
| 119 | * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR ) |
| 120 | * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR ) |
| 121 | * 8/ TQ = Transmit Queue |
| 122 | * 9/ AM = Address Matching Table |
| 123 | * 10/ AP = Address Pointing Table |
| 124 | * |
| 125 | * B. Memory in cache safe RAM to hold |
| 126 | * |
| 127 | * 1/ INT = Interrupt Queue |
| 128 | * 2/ RBD = Receive Buffer Descriptors |
| 129 | * 3/ TBD = Transmit Buffer Descriptors |
| 130 | * |
| 131 | * This function |
| 132 | * 1. clears the ATM DPRAM area, |
| 133 | * 2. Allocates and clears cache safe memory, |
| 134 | * 3. Initializes 'g_conn'. |
| 135 | * |
| 136 | * PARAMETERS: none |
| 137 | * |
| 138 | * RETURNS: OK or ERROR |
| 139 | * |
| 140 | ****************************************************************************/ |
| 141 | int atmMemInit() |
| 142 | { |
| 143 | int i; |
| 144 | unsigned immr = CFG_IMMR; |
| 145 | int total_num_rbd = 0; |
| 146 | int total_num_tbd = 0; |
| 147 | |
| 148 | memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); |
| 149 | |
| 150 | g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; |
| 151 | |
| 152 | for ( i = 0; i < NUM_CONNECTIONS; ++i ) { |
| 153 | total_num_rbd += g_conn[i].num_rbd; |
| 154 | total_num_tbd += g_conn[i].num_tbd; |
| 155 | } |
| 156 | |
| 157 | g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4; |
| 158 | |
| 159 | g_atm.csram = &csram[0]; |
| 160 | memset(&(g_atm.csram), 0x00, g_atm.csram_size); |
| 161 | |
Wolfgang Denk | a566466 | 2008-07-03 23:06:36 +0200 | [diff] [blame] | 162 | g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 163 | g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); |
| 164 | g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); |
| 165 | |
| 166 | g_conn[0].rbd_ptr = g_atm.rbd_base_ptr; |
| 167 | g_conn[0].tbd_ptr = g_atm.tbd_base_ptr; |
| 168 | g_conn[0].ct_ptr = CT_PTR(immr); |
| 169 | g_conn[0].tcte_ptr = TCTE_PTR(immr); |
| 170 | |
| 171 | return OK; |
| 172 | } |
| 173 | |
| 174 | /***************************************************************************** |
| 175 | * |
| 176 | * FUNCTION NAME: atmIntInit |
| 177 | * |
| 178 | * DESCRIPTION: |
| 179 | * |
| 180 | * Initialization of the MPC860 ESAR Interrupt Queue. |
| 181 | * This function |
| 182 | * - clears all entries in the INT, |
| 183 | * - sets the WRAP bit of the last INT entry, |
| 184 | * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure |
| 185 | * to the first INT entry. |
| 186 | * |
| 187 | * PARAMETERS: none |
| 188 | * |
| 189 | * RETURNS: void |
| 190 | * |
| 191 | * REMARKS: |
| 192 | * |
| 193 | * - The INT resides in external cache safe memory. |
| 194 | * - The base address of the INT is stored in g_atm.int_reload_ptr. |
| 195 | * - The number of entries in the INT is given by NUM_INT_ENTRIES. |
| 196 | * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit(). |
| 197 | * |
| 198 | ****************************************************************************/ |
| 199 | void atmIntInit() |
| 200 | { |
| 201 | int i; |
| 202 | for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0; |
| 203 | g_atm.int_reload_ptr[i] = INT_WRAP; |
| 204 | g_atm.int_serv_ptr = g_atm.int_reload_ptr; |
| 205 | } |
| 206 | |
| 207 | /***************************************************************************** |
| 208 | * |
| 209 | * FUNCTION NAME: atmApcInit |
| 210 | * |
| 211 | * DESCRIPTION: |
| 212 | * |
| 213 | * This function initializes the following ATM Pace Controller related |
| 214 | * data structures: |
| 215 | * |
| 216 | * - 1 MPHY Pointing Table (contains only one entry) |
| 217 | * - 3 APC Parameter Tables (one PHY with 3 priorities) |
| 218 | * - 3 APC Tables (one table for each priority) |
| 219 | * - 1 Transmit Queue (one transmit queue per PHY) |
| 220 | * |
| 221 | * PARAMETERS: none |
| 222 | * |
| 223 | * RETURNS: void |
| 224 | * |
| 225 | ****************************************************************************/ |
| 226 | void atmApcInit() |
| 227 | { |
| 228 | int i; |
| 229 | /* unsigned immr = CFG_IMMR; */ |
| 230 | uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR); |
| 231 | struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR); |
| 232 | uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR); |
| 233 | uint16 * tq_ptr = TQ_PTR(CFG_IMMR); |
| 234 | /***************************************************/ |
| 235 | /* Initialize MPHY Pointing Table (only one entry) */ |
| 236 | /***************************************************/ |
| 237 | *mphypt_ptr = APCP_BASE; |
| 238 | |
| 239 | /********************************************/ |
| 240 | /* Initialize APC parameters for priority 1 */ |
| 241 | /********************************************/ |
| 242 | apcp_ptr->apct_base1 = APCT_PRIO_1_BASE; |
| 243 | apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2; |
| 244 | apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE; |
| 245 | apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE; |
| 246 | apcp_ptr->etqbase = TQ_BASE; |
| 247 | apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2; |
| 248 | apcp_ptr->etqaptr = TQ_BASE; |
| 249 | apcp_ptr->etqtptr = TQ_BASE; |
| 250 | apcp_ptr->apc_mi = 8; |
| 251 | apcp_ptr->ncits = 0x0100; /* NCITS = 1 */ |
| 252 | apcp_ptr->apcnt = 0; |
| 253 | apcp_ptr->reserved1 = 0; |
| 254 | apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */ |
| 255 | apcp_ptr->ptp_counter = 0; |
| 256 | apcp_ptr->ptp_txch = 0; |
| 257 | apcp_ptr->reserved2 = 0; |
| 258 | |
| 259 | |
| 260 | /***************************************************/ |
| 261 | /* Initialize APC Tables with empty slots (0xFFFF) */ |
| 262 | /***************************************************/ |
| 263 | for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF; |
| 264 | |
| 265 | /************************/ |
| 266 | /* Clear Transmit Queue */ |
| 267 | /************************/ |
| 268 | for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0; |
| 269 | } |
| 270 | |
| 271 | /***************************************************************************** |
| 272 | * |
| 273 | * FUNCTION NAME: atmAmtInit |
| 274 | * |
| 275 | * DESCRIPTION: |
| 276 | * |
| 277 | * This function clears the first entry in the Address Matching Table and |
| 278 | * lets the first entry in the Address Pointing table point to the first |
| 279 | * entry in the TCT table (i.e. the raw cell channel). |
| 280 | * |
| 281 | * PARAMETERS: none |
| 282 | * |
| 283 | * RETURNS: void |
| 284 | * |
| 285 | * REMARKS: |
| 286 | * |
| 287 | * The values for the AMBASE, AMEND and APBASE registers in SAR parameter |
| 288 | * RAM are initialized by atmCpmInit(). |
| 289 | * |
| 290 | ****************************************************************************/ |
| 291 | void atmAmtInit() |
| 292 | { |
| 293 | unsigned immr = CFG_IMMR; |
| 294 | |
| 295 | g_atm.am_top = AM_PTR(immr); |
| 296 | g_atm.ap_top = AP_PTR(immr); |
| 297 | |
| 298 | *(g_atm.ap_top--) = CT_BASE; |
| 299 | *(g_atm.am_top--) = 0; |
| 300 | } |
| 301 | |
| 302 | /***************************************************************************** |
| 303 | * |
| 304 | * FUNCTION NAME: atmCpmInit |
| 305 | * |
| 306 | * DESCRIPTION: |
| 307 | * |
| 308 | * This function initializes the Utopia Interface Parameter RAM Map |
| 309 | * (SCC4, ATM Protocol) of the Communication Processor Modudule. |
| 310 | * |
| 311 | * PARAMETERS: none |
| 312 | * |
| 313 | * RETURNS: void |
| 314 | * |
| 315 | ****************************************************************************/ |
| 316 | void atmCpmInit() |
| 317 | { |
| 318 | unsigned immr = CFG_IMMR; |
| 319 | |
| 320 | memset((char *)immr + 0x3F00, 0x00, 0xC0); |
| 321 | |
| 322 | /*-----------------------------------------------------------------*/ |
| 323 | /* RBDBASE - Receive buffer descriptors base address */ |
| 324 | /* The RBDs reside in cache safe external memory. */ |
| 325 | /*-----------------------------------------------------------------*/ |
| 326 | *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr; |
| 327 | |
| 328 | /*-----------------------------------------------------------------*/ |
| 329 | /* SRFCR - SAR receive function code */ |
| 330 | /* 0-2 rsvd = 000 */ |
| 331 | /* 3-4 BO = 11 Byte ordering (big endian). */ |
| 332 | /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ |
| 333 | /* when the SDMA channel accesses memory. */ |
| 334 | /*-----------------------------------------------------------------*/ |
| 335 | *SRFCR(immr) = 0x18; |
| 336 | |
| 337 | /*-----------------------------------------------------------------*/ |
| 338 | /* SRSTATE - SAR receive status */ |
| 339 | /* 0 EXT = 0 Extended mode off. */ |
| 340 | /* 1 ACP = 0 Valid only if EXT = 1. */ |
| 341 | /* 2 EC = 0 Standard 53-byte ATM cell. */ |
| 342 | /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */ |
| 343 | /* 4 ESAR = 1 Enhanced SAR functionality enabled. */ |
| 344 | /* 5 MCF = 1 Management Cell Filter active. */ |
| 345 | /* 6 SER = 0 UTOPIA mode. */ |
| 346 | /* 7 MPY = 1 Multiple PHY mode. */ |
| 347 | /*-----------------------------------------------------------------*/ |
| 348 | *SRSTATE(immr) = 0x0D; |
| 349 | |
| 350 | /*-----------------------------------------------------------------*/ |
| 351 | /* MRBLR - Maximum receive buffer length register. */ |
| 352 | /* Must be cleared for ATM operation (see also SMRBLR). */ |
| 353 | /*-----------------------------------------------------------------*/ |
| 354 | *MRBLR(immr) = 0; |
| 355 | |
| 356 | /*-----------------------------------------------------------------*/ |
| 357 | /* RSTATE - SCC internal receive state parameters */ |
| 358 | /* The first byte must be initialized with the value of SRFCR. */ |
| 359 | /*-----------------------------------------------------------------*/ |
| 360 | *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24; |
| 361 | |
| 362 | /*-----------------------------------------------------------------*/ |
| 363 | /* STFCR - SAR transmit function code */ |
| 364 | /* 0-2 rsvd = 000 */ |
| 365 | /* 3-4 BO = 11 Byte ordering (big endian). */ |
| 366 | /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ |
| 367 | /* when the SDMA channel accesses memory. */ |
| 368 | /*-----------------------------------------------------------------*/ |
| 369 | *STFCR(immr) = 0x18; |
| 370 | |
| 371 | /*-----------------------------------------------------------------*/ |
| 372 | /* SRSTATE - SAR transmit status */ |
| 373 | /* 0 EXT = 0 : Extended mode off */ |
| 374 | /* 1 rsvd = 0 : */ |
| 375 | /* 2 EC = 0 : Standard 53-byte ATM cell */ |
| 376 | /* 3 rsvd = 0 : */ |
| 377 | /* 4 ESAR = 1 : Enhanced SAR functionality enabled */ |
| 378 | /* 5 rsvd = 0 : */ |
| 379 | /* 6 SER = 0 : UTOPIA mode */ |
| 380 | /* 7 MPY = 1 : Multiple PHY mode */ |
| 381 | /*-----------------------------------------------------------------*/ |
| 382 | *STSTATE(immr) = 0x09; |
| 383 | |
| 384 | /*-----------------------------------------------------------------*/ |
| 385 | /* TBDBASE - Transmit buffer descriptors base address */ |
| 386 | /* The TBDs reside in cache safe external memory. */ |
| 387 | /*-----------------------------------------------------------------*/ |
| 388 | *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr; |
| 389 | |
| 390 | /*-----------------------------------------------------------------*/ |
| 391 | /* TSTATE - SCC internal transmit state parameters */ |
| 392 | /* The first byte must be initialized with the value of STFCR. */ |
| 393 | /*-----------------------------------------------------------------*/ |
| 394 | *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24; |
| 395 | |
| 396 | /*-----------------------------------------------------------------*/ |
| 397 | /* CTBASE - Connection table base address */ |
| 398 | /* Offset from the beginning of DPRAM (64-byte aligned). */ |
| 399 | /*-----------------------------------------------------------------*/ |
| 400 | *CTBASE(immr) = CT_BASE; |
| 401 | |
| 402 | /*-----------------------------------------------------------------*/ |
| 403 | /* INTBASE - Interrupt queue base pointer. */ |
| 404 | /* The interrupt queue resides in cache safe external memory. */ |
| 405 | /*-----------------------------------------------------------------*/ |
| 406 | *INTBASE(immr) = (uint32)g_atm.int_reload_ptr; |
| 407 | |
| 408 | /*-----------------------------------------------------------------*/ |
| 409 | /* INTPTR - Pointer into interrupt queue. */ |
| 410 | /* Initialize to INTBASE. */ |
| 411 | /*-----------------------------------------------------------------*/ |
| 412 | *INTPTR(immr) = *INTBASE(immr); |
| 413 | |
| 414 | /*-----------------------------------------------------------------*/ |
| 415 | /* C_MASK - Constant mask for CRC32 */ |
| 416 | /* Must be initialized to 0xDEBB20E3. */ |
| 417 | /*-----------------------------------------------------------------*/ |
| 418 | *C_MASK(immr) = 0xDEBB20E3; |
| 419 | |
| 420 | /*-----------------------------------------------------------------*/ |
| 421 | /* INT_ICNT - Interrupt threshold value */ |
| 422 | /*-----------------------------------------------------------------*/ |
| 423 | *INT_ICNT(immr) = 1; |
| 424 | |
| 425 | /*-----------------------------------------------------------------*/ |
| 426 | /* INT_CNT - Interrupt counter */ |
| 427 | /* Initalize to INT_ICNT. Decremented for each interrupt entry */ |
| 428 | /* reported in the interrupt queue. On zero an interrupt is */ |
| 429 | /* signaled to the host by setting the GINT bit in the event */ |
| 430 | /* register. The counter is reinitialized with INT_ICNT. */ |
| 431 | /*-----------------------------------------------------------------*/ |
| 432 | *INT_CNT(immr) = *INT_ICNT(immr); |
| 433 | |
| 434 | /*-----------------------------------------------------------------*/ |
| 435 | /* SMRBLR - SAR maximum receive buffer length register. */ |
| 436 | /* Must be a multiple of 48 bytes. Common for all ATM connections. */ |
| 437 | /*-----------------------------------------------------------------*/ |
| 438 | *SMRBLR(immr) = SAR_RXB_SIZE; |
| 439 | |
| 440 | /*-----------------------------------------------------------------*/ |
| 441 | /* APCST - APC status register. */ |
| 442 | /* 0 rsvd 0 */ |
| 443 | /* 1-2 CSER 11 Initialize with the same value as NSER. */ |
| 444 | /* 3-4 NSER 11 Next serial or UTOPIA channel. */ |
| 445 | /* 5-7 rsvd 000 */ |
| 446 | /* 8-10 rsvd 000 */ |
| 447 | /* 11 rsvd 0 */ |
| 448 | /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */ |
| 449 | /* 13 DIS 0 APC disable. Must be initiazed to 0. */ |
| 450 | /* 14 PL2 0 Not used. */ |
| 451 | /* 15 MPY 1 Multiple PHY mode on. */ |
| 452 | /*-----------------------------------------------------------------*/ |
| 453 | *APCST(immr) = 0x7809; |
| 454 | |
| 455 | /*-----------------------------------------------------------------*/ |
| 456 | /* APCPTR - Pointer to the APC parameter table */ |
| 457 | /* In MPHY master mode this parameter points to the MPHY pointing */ |
| 458 | /* table. 2-byte aligned. */ |
| 459 | /*-----------------------------------------------------------------*/ |
| 460 | *APCPTR(immr) = MPHYPT_BASE; |
| 461 | |
| 462 | /*-----------------------------------------------------------------*/ |
| 463 | /* HMASK - Header mask */ |
| 464 | /* Each incoming cell is masked with HMASK before being compared */ |
| 465 | /* to the entries in the address matching table. */ |
| 466 | /*-----------------------------------------------------------------*/ |
| 467 | *HMASK(immr) = AM_HMASK; |
| 468 | |
| 469 | /*-----------------------------------------------------------------*/ |
| 470 | /* AMBASE - Address matching table base address */ |
| 471 | /*-----------------------------------------------------------------*/ |
| 472 | *AMBASE(immr) = AM_BASE; |
| 473 | |
| 474 | /*-----------------------------------------------------------------*/ |
| 475 | /* AMEND - Address matching table end address */ |
| 476 | /*-----------------------------------------------------------------*/ |
| 477 | *AMEND(immr) = AM_BASE; |
| 478 | |
| 479 | /*-----------------------------------------------------------------*/ |
| 480 | /* APBASE - Address pointing table base address */ |
| 481 | /*-----------------------------------------------------------------*/ |
| 482 | *APBASE(immr) = AP_BASE; |
| 483 | |
| 484 | /*-----------------------------------------------------------------*/ |
| 485 | /* MPHYST - MPHY status register */ |
| 486 | /* 0-1 rsvd 00 */ |
| 487 | /* 2-6 NMPHY 00000 1 PHY */ |
| 488 | /* 7-9 rsvd 000 */ |
| 489 | /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */ |
| 490 | /*-----------------------------------------------------------------*/ |
| 491 | *MPHYST(immr) = 0x0000; |
| 492 | |
| 493 | /*-----------------------------------------------------------------*/ |
| 494 | /* TCTEBASE - Transmit connection table extension base address */ |
| 495 | /* Offset from the beginning of DPRAM (32-byte aligned). */ |
| 496 | /*-----------------------------------------------------------------*/ |
| 497 | *TCTEBASE(immr) = TCTE_BASE; |
| 498 | |
| 499 | /*-----------------------------------------------------------------*/ |
| 500 | /* Clear not used registers. */ |
| 501 | /*-----------------------------------------------------------------*/ |
| 502 | } |
| 503 | |
| 504 | /***************************************************************************** |
| 505 | * |
| 506 | * FUNCTION NAME: atmUtpInit |
| 507 | * |
| 508 | * DESCRIPTION: |
| 509 | * |
| 510 | * This function initializes the ATM interface for |
| 511 | * |
| 512 | * - UTOPIA mode |
| 513 | * - muxed bus |
| 514 | * - master operation |
| 515 | * - multi PHY (because of a bug in the MPC860P rev. E.0) |
| 516 | * - internal clock = SYSCLK / 2 |
| 517 | * |
| 518 | * EXTERNAL EFFECTS: |
| 519 | * |
| 520 | * After calling this function, the MPC860ESAR UTOPIA bus is |
| 521 | * active and uses the following ports/pins: |
| 522 | * |
| 523 | * Port Pin Signal Description |
| 524 | * ------ --- ------- ------------------------------------------- |
| 525 | * PB[15] R17 TxClav Transmit cell available input/output signal |
| 526 | * PC[15] D16 RxClav Receive cell available input/output signal |
| 527 | * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal |
| 528 | * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal |
| 529 | * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal |
| 530 | * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal |
| 531 | * PD[11] T16 RXENB Receive enable input/output signal |
| 532 | * PD[10] W18 TXENB Transmit enable input/output signal |
| 533 | * PD[9] V17 UTPCLK UTOPIA clock input/output signal |
| 534 | * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal |
| 535 | * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal |
| 536 | * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal |
| 537 | * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal |
| 538 | * PD[3] W16 SOC Start of cell input/output signal |
| 539 | * |
| 540 | * PARAMETERS: none |
| 541 | * |
| 542 | * RETURNS: void |
| 543 | * |
| 544 | * REMARK: |
| 545 | * |
| 546 | * The ATM parameters and data structures must be configured before |
| 547 | * initializing the UTOPIA port. The UTOPIA port activates immediately |
| 548 | * upon initialization, and if its associated data structures are not |
| 549 | * initialized, the CPM will lock up. |
| 550 | * |
| 551 | ****************************************************************************/ |
| 552 | void atmUtpInit() |
| 553 | { |
| 554 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 555 | volatile iop8xx_t *iop = &immap->im_ioport; |
| 556 | volatile car8xx_t *car = &immap->im_clkrst; |
| 557 | volatile cpm8xx_t *cpm = &immap->im_cpm; |
| 558 | int flag; |
| 559 | |
| 560 | flag = disable_interrupts(); |
| 561 | |
| 562 | /*-----------------------------------------------------------------*/ |
| 563 | /* SCCR - System Clock Control Register */ |
| 564 | /* */ |
| 565 | /* The UTOPIA clock can be selected to be internal clock or */ |
| 566 | /* external clock (selected by the UTOPIA mode register). */ |
| 567 | /* In case of internal clock, the UTOPIA clock is derived from */ |
| 568 | /* the system frequency divided by two dividers. */ |
| 569 | /* Bits 27-31 of the SCCR register are defined to control the */ |
| 570 | /* UTOPIA clock. */ |
| 571 | /* */ |
| 572 | /* SCCR[27:29] DFUTP Division factor. Divide the system clock */ |
| 573 | /* by 2^DFUTP. */ |
| 574 | /* SCCR[30:31] DFAUTP Additional division factor. Divide the */ |
| 575 | /* system clock by the following value: */ |
| 576 | /* 00 = divide by 1 */ |
| 577 | /* 00 = divide by 3 */ |
| 578 | /* 10 = divide by 5 */ |
| 579 | /* 11 = divide by 7 */ |
| 580 | /* */ |
| 581 | /* Note that the UTOPIA clock must be programmed as to operate */ |
| 582 | /* within the range SYSCLK/10 .. 50Mhz. */ |
| 583 | /*-----------------------------------------------------------------*/ |
| 584 | car->car_sccr &= 0xFFFFFFE0; |
| 585 | car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ |
| 586 | |
| 587 | /*-----------------------------------------------------------------*/ |
| 588 | /* RCCR - RISC Controller Configuration Register */ |
| 589 | /* */ |
| 590 | /* RCCR[8] DR1M IDMA Request 0 Mode */ |
| 591 | /* 0 = edge sensitive */ |
| 592 | /* 1 = level sensitive */ |
| 593 | /* RCCR[9] DR0M IDMA Request 0 Mode */ |
| 594 | /* 0 = edge sensitive */ |
| 595 | /* 1 = level sensitive */ |
| 596 | /* RCCR[10:11] DRQP IDMA Request Priority */ |
| 597 | /* 00 = IDMA req. have more prio. than SCCs */ |
| 598 | /* 01 = IDMA req. have less prio. then SCCs */ |
| 599 | /* 10 = IDMA requests have the lowest prio. */ |
| 600 | /* 11 = reserved */ |
| 601 | /* */ |
| 602 | /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */ |
| 603 | /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */ |
| 604 | /* higher priority. */ |
| 605 | /*-----------------------------------------------------------------*/ |
| 606 | cpm->cp_rccr &= 0xFF0F; |
| 607 | cpm->cp_rccr |= 0x00D0; |
| 608 | |
| 609 | /*-----------------------------------------------------------------*/ |
| 610 | /* Port B - TxClav Signal */ |
| 611 | /*-----------------------------------------------------------------*/ |
| 612 | cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */ |
| 613 | cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */ |
| 614 | |
| 615 | /*-----------------------------------------------------------------*/ |
| 616 | /* UTOPIA Mode Register */ |
| 617 | /* */ |
| 618 | /* - muxed bus (master operation only) */ |
| 619 | /* - multi PHY (because of a bug in the MPC860P rev.E.0) */ |
| 620 | /* - internal clock */ |
| 621 | /* - no loopback */ |
| 622 | /* - do no activate statistical counters */ |
| 623 | /*-----------------------------------------------------------------*/ |
| 624 | iop->utmode = 0x00000004; SYNC; |
| 625 | |
| 626 | /*-----------------------------------------------------------------*/ |
| 627 | /* Port D - UTOPIA Data and Control Signals */ |
| 628 | /* */ |
| 629 | /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */ |
| 630 | /* 11 RXENB UTOPIA receive enable input/output signal */ |
| 631 | /* 10 TXENB UTOPIA transmit enable input/output signal */ |
| 632 | /* 9 TUPCLK UTOPIA clock input/output signal */ |
| 633 | /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */ |
| 634 | /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */ |
| 635 | /* 3 SOC UTOPIA Start of cell input/output signal */ |
| 636 | /* 2 Reserved */ |
| 637 | /* 1 Enable UTOPIA mode */ |
| 638 | /* 0 Enable SAR */ |
| 639 | /*-----------------------------------------------------------------*/ |
| 640 | iop->iop_pdpar |= 0xDF7F; SYNC; |
| 641 | iop->iop_pddir &= 0x2080; SYNC; |
| 642 | |
| 643 | /*-----------------------------------------------------------------*/ |
| 644 | /* Port C - RxClav Signal */ |
| 645 | /*-----------------------------------------------------------------*/ |
| 646 | iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */ |
| 647 | iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */ |
| 648 | iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */ |
| 649 | |
| 650 | if (flag) |
| 651 | enable_interrupts(); |
| 652 | } |