wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000, 2001, 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <mpc8xx.h> |
| 10 | |
| 11 | /* ------------------------------------------------------------------------- */ |
| 12 | const uint sdram_table[] = |
| 13 | { |
| 14 | /*----------------- |
| 15 | UPM A contents: |
| 16 | ----------------- */ |
| 17 | /*--------------------------------------------------- |
| 18 | Read Single Beat Cycle. Offset 0 in the RAM array. |
| 19 | ---------------------------------------------------- */ |
| 20 | 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , |
| 21 | 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , |
| 22 | /*------------------------------------------------ |
| 23 | Read Burst Cycle. Offset 0x8 in the RAM array. |
| 24 | ------------------------------------------------ */ |
| 25 | 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, |
| 26 | 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, |
| 27 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 28 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 29 | /*------------------------------------------------------- |
| 30 | Write Single Beat Cycle. Offset 0x18 in the RAM array |
| 31 | ------------------------------------------------------- */ |
| 32 | 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , |
| 33 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
| 34 | /*------------------------------------------------- |
| 35 | Write Burst Cycle. Offset 0x20 in the RAM array |
| 36 | ------------------------------------------------- */ |
| 37 | 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, |
| 38 | 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, |
| 39 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
| 40 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
| 41 | /*------------------------------------------------------------------------ |
| 42 | Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array |
| 43 | ------------------------------------------------------------------------ */ |
| 44 | 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 45 | 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, |
| 46 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
| 47 | /*----------- |
| 48 | * Exception: |
| 49 | * ----------- */ |
| 50 | 0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , |
| 51 | }; |
| 52 | |
| 53 | /* ------------------------------------------------------------------------- */ |
| 54 | /* |
| 55 | * Check Board Identity: |
| 56 | * |
| 57 | * Test ID string (SVM8...) |
| 58 | * |
| 59 | * Return 1 for "SC8xx" type, 0 else. |
| 60 | */ |
| 61 | |
Wolfgang Denk | f0c0b3a | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 62 | int checkboard(void) |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 63 | { |
Wolfgang Denk | f0c0b3a | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 64 | char buf[64]; |
| 65 | int i; |
| 66 | int l = getenv_f("serial#", buf, sizeof(buf)); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 67 | |
Wolfgang Denk | f0c0b3a | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 68 | if (l < 0 || strncmp(buf, "SVM8", 4)) { |
| 69 | printf("### No HW ID - assuming SVM SC8xx\n"); |
| 70 | return (0); |
| 71 | } |
| 72 | |
Wolfgang Denk | f0c0b3a | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 73 | for (i = 0; i < l; ++i) { |
| 74 | if (buf[i] == ' ') |
| 75 | break; |
| 76 | putc(buf[i]); |
| 77 | } |
| 78 | |
| 79 | putc('\n'); |
| 80 | |
Wolfgang Denk | 13bcd3c | 2011-11-04 15:55:48 +0000 | [diff] [blame] | 81 | return 0; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | /* ------------------------------------------------------------------------- */ |
| 85 | |
Becky Bruce | 9973e3c | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 86 | phys_size_t initdram (int board_type) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 87 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 89 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 90 | long int size_b0 = 0; |
| 91 | |
| 92 | upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
| 93 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 95 | #if defined (CONFIG_SDRAM_16M) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 97 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
| 98 | udelay(1); |
| 99 | memctl->memc_mcr = 0x80002830; |
| 100 | udelay(1); |
| 101 | memctl->memc_mar = 0x00000088; |
| 102 | udelay(1); |
| 103 | memctl->memc_mcr = 0x80002106; |
| 104 | udelay(1); |
| 105 | memctl->memc_or1 = 0xff000a00; |
| 106 | size_b0 = 0x01000000; |
| 107 | #elif defined (CONFIG_SDRAM_32M) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 109 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
| 110 | udelay(1); |
| 111 | memctl->memc_mcr = 0x80002830; |
| 112 | udelay(1); |
| 113 | memctl->memc_mar = 0x00000088; |
| 114 | udelay(1); |
| 115 | memctl->memc_mcr = 0x80002106; |
| 116 | udelay(1); |
| 117 | memctl->memc_or1 = 0xfe000a00; |
| 118 | size_b0 = 0x02000000; |
| 119 | #elif defined (CONFIG_SDRAM_64M) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 120 | memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 121 | memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
| 122 | udelay(1); |
| 123 | memctl->memc_mcr = 0x80002830; |
| 124 | udelay(1); |
| 125 | memctl->memc_mar = 0x00000088; |
| 126 | udelay(1); |
| 127 | memctl->memc_mcr = 0x80002106; |
| 128 | udelay(1); |
| 129 | memctl->memc_or1 = 0xfc000a00; |
| 130 | size_b0 = 0x04000000; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 131 | #else |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 132 | #error SDRAM size configuration missing. |
| 133 | #endif |
| 134 | memctl->memc_br1 = 0x00000081; |
| 135 | udelay(200); |
| 136 | return (size_b0 ); |
| 137 | } |
| 138 | |
Jon Loeliger | ab3abcb | 2007-07-09 18:45:16 -0500 | [diff] [blame] | 139 | #if defined(CONFIG_CMD_DOC) |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 140 | void doc_init (void) |
| 141 | { |
Wolfgang Denk | 93e1459 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 142 | doc_probe (CONFIG_SYS_DOC_BASE); |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 143 | } |
| 144 | #endif |