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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Shinya Kuribayashi282223a2008-03-25 11:43:17 +09002/*
Shinya Kuribayashi282223a2008-03-25 11:43:17 +09003 * Copyright (C) 1996, 99, 2003 by Ralf Baechle
wdenk6069ff22003-02-28 00:49:47 +00004 */
Shinya Kuribayashi282223a2008-03-25 11:43:17 +09005#ifndef _ASM_BYTEORDER_H
6#define _ASM_BYTEORDER_H
wdenk6069ff22003-02-28 00:49:47 +00007
8#include <asm/types.h>
9
10#ifdef __GNUC__
11
Shinya Kuribayashi282223a2008-03-25 11:43:17 +090012#ifdef CONFIG_CPU_MIPSR2
13
14static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
15{
16 __asm__(
17 " wsbh %0, %1 \n"
18 : "=r" (x)
19 : "r" (x));
20
21 return x;
22}
23#define __arch__swab16(x) ___arch__swab16(x)
24
25static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
26{
27 __asm__(
28 " wsbh %0, %1 \n"
29 " rotr %0, %0, 16 \n"
30 : "=r" (x)
31 : "r" (x));
32
33 return x;
34}
35#define __arch__swab32(x) ___arch__swab32(x)
36
37#ifdef CONFIG_CPU_MIPS64_R2
38
39static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
40{
41 __asm__(
42 " dsbh %0, %1 \n"
43 " dshd %0, %0 \n"
44 " drotr %0, %0, 32 \n"
45 : "=r" (x)
46 : "r" (x));
47
48 return x;
49}
50
51#define __arch__swab64(x) ___arch__swab64(x)
52
53#endif /* CONFIG_CPU_MIPS64_R2 */
54
55#endif /* CONFIG_CPU_MIPSR2 */
56
wdenk6069ff22003-02-28 00:49:47 +000057#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
58# define __BYTEORDER_HAS_U64__
59# define __SWAB_64_THRU_32__
60#endif
61
62#endif /* __GNUC__ */
63
Shinya Kuribayashi282223a2008-03-25 11:43:17 +090064#if defined(__MIPSEB__)
wdenk6069ff22003-02-28 00:49:47 +000065# include <linux/byteorder/big_endian.h>
Shinya Kuribayashi282223a2008-03-25 11:43:17 +090066#elif defined(__MIPSEL__)
wdenk6069ff22003-02-28 00:49:47 +000067# include <linux/byteorder/little_endian.h>
68#else
69# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
70#endif
71
Shinya Kuribayashi282223a2008-03-25 11:43:17 +090072#endif /* _ASM_BYTEORDER_H */