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Dirk Behme7379f452009-01-28 21:40:16 +01001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
Dirk Behme7379f452009-01-28 21:40:16 +010031
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
36#define CONFIG_OMAP 1 /* in a TI OMAP core */
37#define CONFIG_OMAP34XX 1 /* which is a 34XX */
38#define CONFIG_OMAP3430 1 /* which is in a 3430 */
39#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
40
41#include <asm/arch/cpu.h> /* get chip and board defs */
42#include <asm/arch/omap3.h>
43
Sanjeev Premi6a6b62e2009-04-27 21:27:27 +053044/*
45 * Display CPU and Board information
46 */
47#define CONFIG_DISPLAY_CPUINFO 1
48#define CONFIG_DISPLAY_BOARDINFO 1
49
Dirk Behme7379f452009-01-28 21:40:16 +010050/* Clock Defines */
51#define V_OSCK 26000000 /* Clock output from T2 */
52#define V_SCLK (V_OSCK >> 1)
53
54#undef CONFIG_USE_IRQ /* no support for IRQs */
55#define CONFIG_MISC_INIT_R
56
57#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58#define CONFIG_SETUP_MEMORY_TAGS 1
59#define CONFIG_INITRD_TAG 1
60#define CONFIG_REVISION_TAG 1
61
62/*
63 * Size of malloc() pool
64 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040065#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Dirk Behme7379f452009-01-28 21:40:16 +010066 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040067#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Dirk Behme7379f452009-01-28 21:40:16 +010068#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
69 /* initial data */
70
71/*
72 * Hardware drivers
73 */
74
75/*
76 * NS16550 Configuration
77 */
78#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
79
80#define CONFIG_SYS_NS16550
81#define CONFIG_SYS_NS16550_SERIAL
82#define CONFIG_SYS_NS16550_REG_SIZE (-4)
83#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
84
85/*
86 * select serial console configuration
87 */
88#define CONFIG_CONS_INDEX 3
89#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90#define CONFIG_SERIAL3 3 /* UART3 */
91
92/* allow to overwrite serial and ethaddr */
93#define CONFIG_ENV_OVERWRITE
94#define CONFIG_BAUDRATE 115200
95#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
96 115200}
97#define CONFIG_MMC 1
98#define CONFIG_OMAP3_MMC 1
99#define CONFIG_DOS_PARTITION 1
100
Nishanth Menon30563a02009-11-07 10:51:24 -0500101/* DDR - I use Micron DDR */
102#define CONFIG_OMAP3_MICRON_DDR 1
103
Tom Rix05be5a62009-10-31 12:37:42 -0500104/* USB */
105#define CONFIG_MUSB_UDC 1
106#define CONFIG_USB_OMAP3 1
107#define CONFIG_TWL4030_USB 1
108
109/* USB device configuration */
110#define CONFIG_USB_DEVICE 1
111#define CONFIG_USB_TTY 1
112#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
113/* Change these to suit your needs */
114#define CONFIG_USBD_VENDORID 0x0451
115#define CONFIG_USBD_PRODUCTID 0x5678
116#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
117#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
118
Dirk Behme7379f452009-01-28 21:40:16 +0100119/* commands to include */
120#include <config_cmd_default.h>
121
122#define CONFIG_CMD_EXT2 /* EXT2 Support */
123#define CONFIG_CMD_FAT /* FAT support */
124#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
125
126#define CONFIG_CMD_I2C /* I2C serial bus support */
127#define CONFIG_CMD_MMC /* MMC support */
128#define CONFIG_CMD_NAND /* NAND support */
Nishanth Menone7deec12009-02-02 18:20:12 -0600129#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
Dirk Behme7379f452009-01-28 21:40:16 +0100130
131#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
132#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
133#undef CONFIG_CMD_IMI /* iminfo */
134#undef CONFIG_CMD_IMLS /* List all found images */
135#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
136#undef CONFIG_CMD_NFS /* NFS support */
137
138#define CONFIG_SYS_NO_FLASH
Tom Rix0297ec72009-09-29 10:19:49 -0400139#define CONFIG_HARD_I2C 1
Dirk Behme7379f452009-01-28 21:40:16 +0100140#define CONFIG_SYS_I2C_SPEED 100000
141#define CONFIG_SYS_I2C_SLAVE 1
142#define CONFIG_SYS_I2C_BUS 0
143#define CONFIG_SYS_I2C_BUS_SELECT 1
144#define CONFIG_DRIVER_OMAP34XX_I2C 1
145
146/*
Tom Rixcd782632009-06-28 12:52:29 -0500147 * TWL4030
148 */
149#define CONFIG_TWL4030_POWER 1
Tom Rix2c155132009-06-28 12:52:30 -0500150#define CONFIG_TWL4030_LED 1
Tom Rixcd782632009-06-28 12:52:29 -0500151
152/*
Dirk Behme7379f452009-01-28 21:40:16 +0100153 * Board NAND Info.
154 */
155#define CONFIG_NAND_OMAP_GPMC
156#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
157 /* to access nand */
158#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
159 /* to access nand at */
160 /* CS0 */
161#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
162
163#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
164 /* devices */
Dirk Behme7379f452009-01-28 21:40:16 +0100165#define CONFIG_JFFS2_NAND
166/* nand device jffs2 lives on */
167#define CONFIG_JFFS2_DEV "nand0"
168/* start of jffs2 partition */
169#define CONFIG_JFFS2_PART_OFFSET 0x680000
170#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
171 /* partition */
172
173/* Environment information */
174#define CONFIG_BOOTDELAY 10
175
176#define CONFIG_EXTRA_ENV_SETTINGS \
177 "loadaddr=0x82000000\0" \
Tom Rix05be5a62009-10-31 12:37:42 -0500178 "usbtty=cdc_acm\0" \
Dirk Behme7379f452009-01-28 21:40:16 +0100179 "console=ttyS2,115200n8\0" \
180 "videomode=1024x768@60,vxres=1024,vyres=768\0" \
181 "videospec=omapfb:vram:2M,vram:4M\0" \
182 "mmcargs=setenv bootargs console=${console} " \
183 "video=${videospec},mode:${videomode} " \
184 "root=/dev/mmcblk0p2 rw " \
185 "rootfstype=ext3 rootwait\0" \
186 "nandargs=setenv bootargs console=${console} " \
187 "video=${videospec},mode:${videomode} " \
188 "root=/dev/mtdblock4 rw " \
189 "rootfstype=jffs2\0" \
190 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
191 "bootscript=echo Running bootscript from mmc ...; " \
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200192 "source ${loadaddr}\0" \
Dirk Behme7379f452009-01-28 21:40:16 +0100193 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
194 "mmcboot=echo Booting from mmc ...; " \
195 "run mmcargs; " \
196 "bootm ${loadaddr}\0" \
197 "nandboot=echo Booting from nand ...; " \
198 "run nandargs; " \
199 "nand read ${loadaddr} 280000 400000; " \
200 "bootm ${loadaddr}\0" \
201
202#define CONFIG_BOOTCOMMAND \
Dirk Behmea85693b2009-04-21 17:30:51 +0200203 "if mmc init; then " \
Dirk Behme7379f452009-01-28 21:40:16 +0100204 "if run loadbootscript; then " \
205 "run bootscript; " \
206 "else " \
207 "if run loaduimage; then " \
208 "run mmcboot; " \
209 "else run nandboot; " \
210 "fi; " \
211 "fi; " \
212 "else run nandboot; fi"
213
214#define CONFIG_AUTO_COMPLETE 1
215/*
216 * Miscellaneous configurable options
217 */
Dirk Behme7379f452009-01-28 21:40:16 +0100218#define CONFIG_SYS_LONGHELP /* undef to save memory */
219#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
220#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500221#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
Dirk Behme7379f452009-01-28 21:40:16 +0100222#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
223/* Print Buffer Size */
224#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
225 sizeof(CONFIG_SYS_PROMPT) + 16)
226#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
227/* Boot Argument Buffer Size */
228#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
229
230#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
231 /* works on */
232#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
233 0x01F00000) /* 31MB */
234
Dirk Behme7379f452009-01-28 21:40:16 +0100235#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
236 /* load address */
237
238/*
Manikandan Pillaid3a513c2009-04-21 17:29:05 +0200239 * OMAP3 has 12 GP timers, they can be driven by the system clock
240 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
241 * This rate is divided by a local divisor.
Dirk Behme7379f452009-01-28 21:40:16 +0100242 */
Manikandan Pillaid3a513c2009-04-21 17:29:05 +0200243#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
244#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
245#define CONFIG_SYS_HZ 1000
Dirk Behme7379f452009-01-28 21:40:16 +0100246
247/*-----------------------------------------------------------------------
248 * Stack sizes
249 *
250 * The stack sizes are set up in start.S using the settings below
251 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400252#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Dirk Behme7379f452009-01-28 21:40:16 +0100253#ifdef CONFIG_USE_IRQ
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400254#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
255#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Dirk Behme7379f452009-01-28 21:40:16 +0100256#endif
257
258/*-----------------------------------------------------------------------
259 * Physical Memory Map
260 */
261#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
262#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400263#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
Dirk Behme7379f452009-01-28 21:40:16 +0100264#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
265
266/* SDRAM Bank Allocation method */
267#define SDRC_R_B_C 1
268
269/*-----------------------------------------------------------------------
270 * FLASH and environment organization
271 */
272
273/* **** PISMO SUPPORT *** */
274
275/* Configure the PISMO */
276#define PISMO1_NAND_SIZE GPMC_SIZE_128M
277#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
278
279#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
280 /* one chip */
281#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400282#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Dirk Behme7379f452009-01-28 21:40:16 +0100283
284#define CONFIG_SYS_FLASH_BASE boot_flash_base
285
286/* Monitor at start of flash */
287#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
288#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
289
290#define CONFIG_ENV_IS_IN_NAND 1
291#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
292#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
293
294#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
295#define CONFIG_ENV_OFFSET boot_flash_off
296#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
297
298/*-----------------------------------------------------------------------
299 * CFI FLASH driver setup
300 */
301/* timeout values are in ticks */
302#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
303#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
304
305/* Flash banks JFFS2 should use */
306#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
307 CONFIG_SYS_MAX_NAND_DEVICE)
308#define CONFIG_SYS_JFFS2_MEM_NAND
309/* use flash_info[2] */
310#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
311#define CONFIG_SYS_JFFS2_NUM_BANKS 1
312
313#ifndef __ASSEMBLY__
Dirk Behme7379f452009-01-28 21:40:16 +0100314extern unsigned int boot_flash_base;
315extern volatile unsigned int boot_flash_env_addr;
316extern unsigned int boot_flash_off;
317extern unsigned int boot_flash_sec;
318extern unsigned int boot_flash_type;
319#endif
320
Dirk Behme7379f452009-01-28 21:40:16 +0100321#endif /* __CONFIG_H */