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Minkyu Kangdd2c9e62009-10-01 17:20:28 +09001/*
2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
5 *
6 * based on drivers/serial/s3c64xx.c
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kangdd2c9e62009-10-01 17:20:28 +09009 */
10
11#include <common.h>
Simon Glass73e256c2014-09-14 16:36:17 -060012#include <dm.h>
13#include <errno.h>
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053014#include <fdtdec.h>
Mike Frysinger6c768ca2011-04-29 18:03:29 +000015#include <linux/compiler.h>
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090016#include <asm/io.h>
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090017#include <asm/arch/clk.h>
Simon Glass89ca9352015-07-02 18:15:53 -060018#include <asm/arch/uart.h>
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090019#include <serial.h>
Thomas Abrahamcf75cdf2016-04-23 22:18:11 +053020#include <clk.h>
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090021
John Rigby29565322010-12-20 18:27:51 -070022DECLARE_GLOBAL_DATA_PTR;
23
Simon Glass73e256c2014-09-14 16:36:17 -060024#define RX_FIFO_COUNT_SHIFT 0
25#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
26#define RX_FIFO_FULL (1 << 8)
27#define TX_FIFO_COUNT_SHIFT 16
28#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
29#define TX_FIFO_FULL (1 << 24)
Akshay Saraswatffbff1d2013-03-21 20:33:04 +000030
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053031/* Information about a serial port */
Simon Glass73e256c2014-09-14 16:36:17 -060032struct s5p_serial_platdata {
33 struct s5p_uart *reg; /* address of registers in physical memory */
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053034 u8 port_id; /* uart port number */
Simon Glass73e256c2014-09-14 16:36:17 -060035};
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090036
37/*
Minkyu Kang46a3b5c2010-03-24 16:59:30 +090038 * The coefficient, used to calculate the baudrate on S5P UARTs is
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090039 * calculated as
40 * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
41 * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
42 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
43 */
44static const int udivslot[] = {
45 0,
46 0x0080,
47 0x0808,
48 0x0888,
49 0x2222,
50 0x4924,
51 0x4a52,
52 0x54aa,
53 0x5555,
54 0xd555,
55 0xd5d5,
56 0xddd5,
57 0xdddd,
58 0xdfdd,
59 0xdfdf,
60 0xffdf,
61};
62
Simon Glass89ca9352015-07-02 18:15:53 -060063static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090064{
Simon Glass89ca9352015-07-02 18:15:53 -060065 /* enable FIFOs, auto clear Rx FIFO */
66 writel(0x3, &uart->ufcon);
67 writel(0, &uart->umcon);
68 /* 8N1 */
69 writel(0x3, &uart->ulcon);
70 /* No interrupts, no DMA, pure polling */
71 writel(0x245, &uart->ucon);
72}
73
74static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
75 int baudrate)
76{
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090077 u32 val;
78
Minkyu Kangf70409a2010-08-24 15:51:55 +090079 val = uclk / baudrate;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090080
81 writel(val / 16 - 1, &uart->ubrdiv);
Minkyu Kang1628cfc2010-09-28 14:35:02 +090082
Minkyu Kange0617c62011-01-24 14:43:25 +090083 if (s5p_uart_divslot())
Minkyu Kang1628cfc2010-09-28 14:35:02 +090084 writew(udivslot[val % 16], &uart->rest.slot);
85 else
86 writeb(val % 16, &uart->rest.value);
Simon Glass89ca9352015-07-02 18:15:53 -060087}
88
Simon Glass7fb57392015-07-02 18:15:55 -060089#ifndef CONFIG_SPL_BUILD
Simon Glass89ca9352015-07-02 18:15:53 -060090int s5p_serial_setbrg(struct udevice *dev, int baudrate)
91{
92 struct s5p_serial_platdata *plat = dev->platdata;
93 struct s5p_uart *const uart = plat->reg;
Thomas Abrahamcf75cdf2016-04-23 22:18:11 +053094 u32 uclk;
95
96#ifdef CONFIG_CLK_EXYNOS
Stephen Warren135aa952016-06-17 09:44:00 -060097 struct clk clk;
Thomas Abrahamcf75cdf2016-04-23 22:18:11 +053098 u32 ret;
99
Stephen Warren135aa952016-06-17 09:44:00 -0600100 ret = clk_get_by_index(dev, 1, &clk);
Thomas Abrahamcf75cdf2016-04-23 22:18:11 +0530101 if (ret < 0)
102 return ret;
Stephen Warren135aa952016-06-17 09:44:00 -0600103 uclk = clk_get_rate(&clk);
Thomas Abrahamcf75cdf2016-04-23 22:18:11 +0530104#else
105 uclk = get_uart_clk(plat->port_id);
106#endif
Simon Glass89ca9352015-07-02 18:15:53 -0600107
108 s5p_serial_baud(uart, uclk, baudrate);
Simon Glass73e256c2014-09-14 16:36:17 -0600109
110 return 0;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900111}
112
Simon Glass73e256c2014-09-14 16:36:17 -0600113static int s5p_serial_probe(struct udevice *dev)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900114{
Simon Glass73e256c2014-09-14 16:36:17 -0600115 struct s5p_serial_platdata *plat = dev->platdata;
116 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900117
Simon Glass89ca9352015-07-02 18:15:53 -0600118 s5p_serial_init(uart);
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900119
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900120 return 0;
121}
122
Simon Glass73e256c2014-09-14 16:36:17 -0600123static int serial_err_check(const struct s5p_uart *const uart, int op)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900124{
Minkyu Kang94003222009-11-10 20:23:50 +0900125 unsigned int mask;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900126
Minkyu Kang94003222009-11-10 20:23:50 +0900127 /*
128 * UERSTAT
129 * Break Detect [3]
130 * Frame Err [2] : receive operation
131 * Parity Err [1] : receive operation
132 * Overrun Err [0] : receive operation
133 */
134 if (op)
135 mask = 0x8;
136 else
137 mask = 0xf;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900138
Minkyu Kang94003222009-11-10 20:23:50 +0900139 return readl(&uart->uerstat) & mask;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900140}
141
Simon Glass73e256c2014-09-14 16:36:17 -0600142static int s5p_serial_getc(struct udevice *dev)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900143{
Simon Glass73e256c2014-09-14 16:36:17 -0600144 struct s5p_serial_platdata *plat = dev->platdata;
145 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900146
Simon Glass73e256c2014-09-14 16:36:17 -0600147 if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
148 return -EAGAIN;
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530149
Simon Glass73e256c2014-09-14 16:36:17 -0600150 serial_err_check(uart, 0);
Minkyu Kang1a4106d2010-07-06 20:08:29 +0900151 return (int)(readb(&uart->urxh) & 0xff);
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900152}
153
Simon Glass73e256c2014-09-14 16:36:17 -0600154static int s5p_serial_putc(struct udevice *dev, const char ch)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900155{
Simon Glass73e256c2014-09-14 16:36:17 -0600156 struct s5p_serial_platdata *plat = dev->platdata;
157 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900158
Simon Glass73e256c2014-09-14 16:36:17 -0600159 if (readl(&uart->ufstat) & TX_FIFO_FULL)
160 return -EAGAIN;
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530161
Simon Glass73e256c2014-09-14 16:36:17 -0600162 writeb(ch, &uart->utxh);
163 serial_err_check(uart, 1);
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530164
165 return 0;
166}
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530167
Simon Glass73e256c2014-09-14 16:36:17 -0600168static int s5p_serial_pending(struct udevice *dev, bool input)
Mike Frysinger6c768ca2011-04-29 18:03:29 +0000169{
Simon Glass73e256c2014-09-14 16:36:17 -0600170 struct s5p_serial_platdata *plat = dev->platdata;
171 struct s5p_uart *const uart = plat->reg;
172 uint32_t ufstat = readl(&uart->ufstat);
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530173
Simon Glass73e256c2014-09-14 16:36:17 -0600174 if (input)
175 return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
176 else
177 return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
Mike Frysinger6c768ca2011-04-29 18:03:29 +0000178}
Marek Vasutb4980512012-09-12 19:39:57 +0200179
Simon Glass73e256c2014-09-14 16:36:17 -0600180static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
Marek Vasutb4980512012-09-12 19:39:57 +0200181{
Simon Glass73e256c2014-09-14 16:36:17 -0600182 struct s5p_serial_platdata *plat = dev->platdata;
183 fdt_addr_t addr;
184
Simon Glass4e9838c2015-08-11 08:33:29 -0600185 addr = dev_get_addr(dev);
Simon Glass73e256c2014-09-14 16:36:17 -0600186 if (addr == FDT_ADDR_T_NONE)
187 return -EINVAL;
188
189 plat->reg = (struct s5p_uart *)addr;
Simon Glasse160f7d2017-01-17 16:52:55 -0700190 plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Thomas Abraham5ab6c4d2016-04-23 22:18:10 +0530191 "id", dev->seq);
Simon Glass73e256c2014-09-14 16:36:17 -0600192 return 0;
Marek Vasutb4980512012-09-12 19:39:57 +0200193}
Simon Glass73e256c2014-09-14 16:36:17 -0600194
195static const struct dm_serial_ops s5p_serial_ops = {
196 .putc = s5p_serial_putc,
197 .pending = s5p_serial_pending,
198 .getc = s5p_serial_getc,
199 .setbrg = s5p_serial_setbrg,
200};
201
202static const struct udevice_id s5p_serial_ids[] = {
203 { .compatible = "samsung,exynos4210-uart" },
204 { }
205};
206
207U_BOOT_DRIVER(serial_s5p) = {
208 .name = "serial_s5p",
209 .id = UCLASS_SERIAL,
210 .of_match = s5p_serial_ids,
211 .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
212 .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
213 .probe = s5p_serial_probe,
214 .ops = &s5p_serial_ops,
215 .flags = DM_FLAG_PRE_RELOC,
216};
Simon Glass7fb57392015-07-02 18:15:55 -0600217#endif
Simon Glassbf6e7022015-07-02 18:15:54 -0600218
219#ifdef CONFIG_DEBUG_UART_S5P
220
221#include <debug_uart.h>
222
Simon Glass97b05972015-10-18 19:51:23 -0600223static inline void _debug_uart_init(void)
Simon Glassbf6e7022015-07-02 18:15:54 -0600224{
225 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
226
227 s5p_serial_init(uart);
228 s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
229}
230
231static inline void _debug_uart_putc(int ch)
232{
233 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
234
235 while (readl(&uart->ufstat) & TX_FIFO_FULL);
236
237 writeb(ch, &uart->utxh);
238}
239
240DEBUG_UART_FUNCS
241
242#endif