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MengDongyangb44566c2016-08-24 12:02:17 +08001/*
2 * Copyright (c) 2016 Rockchip, Inc.
3 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7#include <common.h>
8#include <dm.h>
MengDongyangb44566c2016-08-24 12:02:17 +08009#include <malloc.h>
10#include <usb.h>
11#include <watchdog.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090012#include <linux/errno.h>
MengDongyangb44566c2016-08-24 12:02:17 +080013#include <linux/compat.h>
14#include <linux/usb/dwc3.h>
Meng Dongyangd3cb14b2017-06-01 19:22:45 +080015#include <power/regulator.h>
MengDongyangb44566c2016-08-24 12:02:17 +080016
17#include "xhci.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21struct rockchip_xhci_platdata {
22 fdt_addr_t hcd_base;
23 fdt_addr_t phy_base;
Meng Dongyangd3cb14b2017-06-01 19:22:45 +080024 struct udevice *vbus_supply;
MengDongyangb44566c2016-08-24 12:02:17 +080025};
26
27/*
28 * Contains pointers to register base addresses
29 * for the usb controller.
30 */
31struct rockchip_xhci {
32 struct usb_platdata usb_plat;
33 struct xhci_ctrl ctrl;
34 struct xhci_hccr *hcd;
35 struct dwc3 *dwc3_reg;
36};
37
38static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
39{
40 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
41 struct udevice *child;
42 int ret = 0;
43
44 /*
45 * Get the base address for XHCI controller from the device node
46 */
Philipp Tomsich32c8eee2017-09-12 17:32:25 +020047 plat->hcd_base = dev_read_addr(dev);
MengDongyangb44566c2016-08-24 12:02:17 +080048 if (plat->hcd_base == FDT_ADDR_T_NONE) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090049 pr_err("Can't get the XHCI register base address\n");
MengDongyangb44566c2016-08-24 12:02:17 +080050 return -ENXIO;
51 }
52
53 /* Get the base address for usbphy from the device node */
54 for (device_find_first_child(dev, &child); child;
55 device_find_next_child(&child)) {
Simon Glass911f3ae2017-05-18 20:08:57 -060056 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
MengDongyangb44566c2016-08-24 12:02:17 +080057 continue;
Simon Glassa821c4a2017-05-17 17:18:05 -060058 plat->phy_base = devfdt_get_addr(child);
MengDongyangb44566c2016-08-24 12:02:17 +080059 break;
60 }
61
62 if (plat->phy_base == FDT_ADDR_T_NONE) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090063 pr_err("Can't get the usbphy register address\n");
MengDongyangb44566c2016-08-24 12:02:17 +080064 return -ENXIO;
65 }
66
Meng Dongyangd3cb14b2017-06-01 19:22:45 +080067 /* Vbus regulator */
68 ret = device_get_supply_regulator(dev, "vbus-supply",
69 &plat->vbus_supply);
MengDongyangb44566c2016-08-24 12:02:17 +080070 if (ret)
Meng Dongyang26a8b802017-06-28 19:22:40 +080071 debug("Can't get VBus regulator!\n");
MengDongyangb44566c2016-08-24 12:02:17 +080072
73 return 0;
74}
75
76/*
77 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
78 * @dwc: Pointer to our controller context structure
79 * @dev: Pointer to ulcass device
80 */
81static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
82 struct udevice *dev)
83{
84 u32 reg;
MengDongyangb44566c2016-08-24 12:02:17 +080085 u32 utmi_bits;
86
87 /* Set dwc3 usb2 phy config */
88 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
89
Philipp Tomsichf2708c92017-06-07 18:45:59 +020090 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
MengDongyangb44566c2016-08-24 12:02:17 +080091 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
92
Philipp Tomsichf2708c92017-06-07 18:45:59 +020093 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
MengDongyangb44566c2016-08-24 12:02:17 +080094 if (utmi_bits == 16) {
95 reg |= DWC3_GUSB2PHYCFG_PHYIF;
96 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
97 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
98 } else if (utmi_bits == 8) {
99 reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
100 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
101 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
102 }
103
Philipp Tomsichf2708c92017-06-07 18:45:59 +0200104 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
MengDongyangb44566c2016-08-24 12:02:17 +0800105 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
106
Philipp Tomsichf2708c92017-06-07 18:45:59 +0200107 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
MengDongyangb44566c2016-08-24 12:02:17 +0800108 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
109
110 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
111}
112
113static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
114 struct udevice *dev)
115{
116 int ret;
117
118 ret = dwc3_core_init(rkxhci->dwc3_reg);
119 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900120 pr_err("failed to initialize core\n");
MengDongyangb44566c2016-08-24 12:02:17 +0800121 return ret;
122 }
123
124 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
125
126 /* We are hard-coding DWC3 core to Host Mode */
127 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
128
129 return 0;
130}
131
132static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
133{
134 return 0;
135}
136
137static int xhci_usb_probe(struct udevice *dev)
138{
139 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
140 struct rockchip_xhci *ctx = dev_get_priv(dev);
141 struct xhci_hcor *hcor;
142 int ret;
143
144 ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
145 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
146 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
147 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
148
Meng Dongyang26a8b802017-06-28 19:22:40 +0800149 if (plat->vbus_supply) {
150 ret = regulator_set_enable(plat->vbus_supply, true);
151 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900152 pr_err("XHCI: failed to set VBus supply\n");
Meng Dongyang26a8b802017-06-28 19:22:40 +0800153 return ret;
154 }
155 }
MengDongyangb44566c2016-08-24 12:02:17 +0800156
157 ret = rockchip_xhci_core_init(ctx, dev);
158 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900159 pr_err("XHCI: failed to initialize controller\n");
MengDongyangb44566c2016-08-24 12:02:17 +0800160 return ret;
161 }
162
163 return xhci_register(dev, ctx->hcd, hcor);
164}
165
166static int xhci_usb_remove(struct udevice *dev)
167{
Meng Dongyangd3cb14b2017-06-01 19:22:45 +0800168 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
MengDongyangb44566c2016-08-24 12:02:17 +0800169 struct rockchip_xhci *ctx = dev_get_priv(dev);
170 int ret;
171
172 ret = xhci_deregister(dev);
173 if (ret)
174 return ret;
175 ret = rockchip_xhci_core_exit(ctx);
176 if (ret)
177 return ret;
178
Meng Dongyang26a8b802017-06-28 19:22:40 +0800179 if (plat->vbus_supply) {
180 ret = regulator_set_enable(plat->vbus_supply, false);
181 if (ret)
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900182 pr_err("XHCI: failed to set VBus supply\n");
Meng Dongyang26a8b802017-06-28 19:22:40 +0800183 }
Meng Dongyangd3cb14b2017-06-01 19:22:45 +0800184
Meng Dongyang26a8b802017-06-28 19:22:40 +0800185 return ret;
MengDongyangb44566c2016-08-24 12:02:17 +0800186}
187
188static const struct udevice_id xhci_usb_ids[] = {
189 { .compatible = "rockchip,rk3399-xhci" },
Meng Dongyangd3cb14b2017-06-01 19:22:45 +0800190 { .compatible = "rockchip,rk3328-xhci" },
MengDongyangb44566c2016-08-24 12:02:17 +0800191 { }
192};
193
194U_BOOT_DRIVER(usb_xhci) = {
195 .name = "xhci_rockchip",
196 .id = UCLASS_USB,
197 .of_match = xhci_usb_ids,
198 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
199 .probe = xhci_usb_probe,
200 .remove = xhci_usb_remove,
201 .ops = &xhci_usb_ops,
202 .bind = dm_scan_fdt_dev,
203 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
204 .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
205 .flags = DM_FLAG_ALLOC_PRIV_DMA,
206};
207
208static const struct udevice_id usb_phy_ids[] = {
209 { .compatible = "rockchip,rk3399-usb3-phy" },
Meng Dongyangd3cb14b2017-06-01 19:22:45 +0800210 { .compatible = "rockchip,rk3328-usb3-phy" },
MengDongyangb44566c2016-08-24 12:02:17 +0800211 { }
212};
213
214U_BOOT_DRIVER(usb_phy) = {
215 .name = "usb_phy_rockchip",
216 .of_match = usb_phy_ids,
217};