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wdenkd9fd6ff2002-10-11 08:43:32 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
Ben Warren1ab70f62009-12-14 16:30:39 -080029#include <netdev.h>
Marek Vasut4438a452011-11-26 11:17:32 +010030#include <asm/arch/pxa.h>
Marek Vasute570fe82011-12-12 05:34:03 +000031#include <asm/arch/pxa-regs.h>
32#include <asm/io.h>
wdenkd9fd6ff2002-10-11 08:43:32 +000033
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
wdenkd9fd6ff2002-10-11 08:43:32 +000035
36/*
37 * Miscelaneous platform dependent initialisations
38 */
39
40int board_init (void)
41{
Marek Vasut3c43ca22010-10-20 20:55:44 +020042 /* We have RAM, disable cache */
43 dcache_disable();
44 icache_disable();
wdenkd9fd6ff2002-10-11 08:43:32 +000045
46 /* arch number of Lubbock-Board */
wdenk731215e2004-10-10 18:41:04 +000047 gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
wdenkd9fd6ff2002-10-11 08:43:32 +000048
49 /* adress of boot parameters */
50 gd->bd->bi_boot_params = 0xa0000100;
51
Marek Vasute570fe82011-12-12 05:34:03 +000052 /* Configure GPIO6 and GPIO8 as OUT, AF1. */
53 setbits_le32(GPDR0, (1 << 6) | (1 << 8));
54 clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16));
55
wdenkdb2f721f2003-03-06 00:58:30 +000056 return 0;
wdenkd9fd6ff2002-10-11 08:43:32 +000057}
58
wdenkc837dcb2004-01-20 23:12:12 +000059int board_late_init(void)
wdenk71f95112003-06-15 22:40:42 +000060{
wdenkc837dcb2004-01-20 23:12:12 +000061 setenv("stdout", "serial");
62 setenv("stderr", "serial");
wdenk71f95112003-06-15 22:40:42 +000063 return 0;
64}
65
Marek Vasut3c43ca22010-10-20 20:55:44 +020066int dram_init(void)
67{
Marek Vasutf68d2a22011-11-26 11:18:57 +010068 pxa2xx_dram_init();
Marek Vasut3c43ca22010-10-20 20:55:44 +020069 gd->ram_size = PHYS_SDRAM_1_SIZE;
70 return 0;
71}
wdenk71f95112003-06-15 22:40:42 +000072
Marek Vasut3c43ca22010-10-20 20:55:44 +020073void dram_init_banksize(void)
wdenkd9fd6ff2002-10-11 08:43:32 +000074{
wdenkd9fd6ff2002-10-11 08:43:32 +000075 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
76 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
wdenkd9fd6ff2002-10-11 08:43:32 +000077}
Ben Warren1ab70f62009-12-14 16:30:39 -080078
79#ifdef CONFIG_CMD_NET
80int board_eth_init(bd_t *bis)
81{
82 int rc = 0;
83#ifdef CONFIG_LAN91C96
84 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
85#endif
86 return rc;
87}
88#endif