| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 |
| 3 | * Marvell Semiconductor <www.marvell.com> |
| 4 | * Written-by: Lei Wen <leiwen@marvell.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * This file should be included in board config header file. |
| 11 | * |
| Stefan Roese | f7c0ef0 | 2015-04-25 06:29:49 +0200 | [diff] [blame] | 12 | * It supports common definitions for MVEBU platforms |
| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| Stefan Roese | 250eea7 | 2015-04-25 06:29:47 +0200 | [diff] [blame] | 15 | #ifndef _MVEBU_CONFIG_H |
| 16 | #define _MVEBU_CONFIG_H |
| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 17 | |
| 18 | #include <asm/arch/soc.h> |
| 19 | |
| Stefan Roese | f7c0ef0 | 2015-04-25 06:29:49 +0200 | [diff] [blame] | 20 | #if defined(CONFIG_ARMADA_XP) |
| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 21 | #define MV88F78X60 /* for the DDR training bin_hdr code */ |
| Stefan Roese | f7c0ef0 | 2015-04-25 06:29:49 +0200 | [diff] [blame] | 22 | #endif |
| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 23 | |
| 24 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 25 | |
| 26 | /* |
| 27 | * By default kwbimage.cfg from board specific folder is used |
| 28 | * If for some board, different configuration file need to be used, |
| 29 | * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file |
| 30 | */ |
| 31 | #ifndef CONFIG_SYS_KWD_CONFIG |
| 32 | #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg |
| 33 | #endif /* CONFIG_SYS_KWD_CONFIG */ |
| 34 | |
| 35 | /* Add target to build it automatically upon "make" */ |
| Stefan Roese | 1e0b598 | 2015-01-19 11:33:49 +0100 | [diff] [blame] | 36 | #ifdef CONFIG_SPL |
| 37 | #define CONFIG_BUILD_TARGET "u-boot-spl.kwb" |
| Stefan Roese | 1e0b598 | 2015-01-19 11:33:49 +0100 | [diff] [blame] | 38 | #endif |
| Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 39 | |
| 40 | /* end of 16M scrubbed by training in bootrom */ |
| 41 | #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 |
| 42 | #define CONFIG_NR_DRAM_BANKS_MAX 2 |
| 43 | |
| 44 | #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE |
| 45 | |
| 46 | /* |
| 47 | * SPI Flash configuration |
| 48 | */ |
| 49 | #ifdef CONFIG_CMD_SF |
| 50 | #define CONFIG_HARD_SPI 1 |
| 51 | #define CONFIG_KIRKWOOD_SPI 1 |
| 52 | #ifndef CONFIG_ENV_SPI_BUS |
| 53 | # define CONFIG_ENV_SPI_BUS 0 |
| 54 | #endif |
| 55 | #ifndef CONFIG_ENV_SPI_CS |
| 56 | # define CONFIG_ENV_SPI_CS 0 |
| 57 | #endif |
| 58 | #ifndef CONFIG_ENV_SPI_MAX_HZ |
| 59 | # define CONFIG_ENV_SPI_MAX_HZ 50000000 |
| 60 | #endif |
| 61 | #endif |
| 62 | |
| 63 | /* |
| 64 | * Ethernet Driver configuration |
| 65 | */ |
| 66 | #ifdef CONFIG_CMD_NET |
| 67 | #define CONFIG_CMD_MII |
| 68 | #define CONFIG_MII /* expose smi ove miiphy interface */ |
| 69 | #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ |
| 70 | #define CONFIG_PHYLIB |
| 71 | #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ |
| 72 | #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ |
| 73 | #endif /* CONFIG_CMD_NET */ |
| 74 | |
| 75 | /* |
| 76 | * I2C related stuff |
| 77 | */ |
| 78 | #ifdef CONFIG_CMD_I2C |
| 79 | #ifndef CONFIG_SYS_I2C_SOFT |
| 80 | #define CONFIG_I2C_MVTWSI |
| 81 | #endif |
| 82 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 83 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 84 | #endif |
| 85 | |
| Stefan Roese | 880b15a | 2015-04-25 06:29:50 +0200 | [diff] [blame] | 86 | /* Common SPL configuration */ |
| 87 | #ifndef CONFIG_SPL_LDSCRIPT |
| 88 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds" |
| 89 | #endif |
| 90 | |
| Stefan Roese | 250eea7 | 2015-04-25 06:29:47 +0200 | [diff] [blame] | 91 | #endif /* __MVEBU_CONFIG_H */ |