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Sricharan508a58f2011-11-15 09:49:55 -05001/*
2 *
3 * Functions for omap5 based boards.
4 *
5 * (C) Copyright 2011
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 * Sricharan <r.sricharan@ti.com>
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Sricharan508a58f2011-11-15 09:49:55 -050014 */
15#include <common.h>
16#include <asm/armv7.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/sys_proto.h>
Lokesh Vutlaaf1d0022013-05-30 02:54:32 +000019#include <asm/arch/clock.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040020#include <linux/sizes.h>
Sricharan508a58f2011-11-15 09:49:55 -050021#include <asm/utils.h>
22#include <asm/arch/gpio.h>
Lokesh Vutla784ab7c2012-05-22 00:03:25 +000023#include <asm/emif.h>
SRICHARAN Rf92f2272013-04-24 00:41:22 +000024#include <asm/omap_common.h>
Sricharan508a58f2011-11-15 09:49:55 -050025
26DECLARE_GLOBAL_DATA_PTR;
27
SRICHARAN Rf92f2272013-04-24 00:41:22 +000028u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
Sricharan508a58f2011-11-15 09:49:55 -050029
Axel Lin87bd05d2013-06-21 18:54:25 +080030static struct gpio_bank gpio_bank_54xx[8] = {
Sricharan508a58f2011-11-15 09:49:55 -050031 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
32 { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
33 { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
34 { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
35 { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
36 { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
Axel Lin87bd05d2013-06-21 18:54:25 +080037 { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
38 { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
Sricharan508a58f2011-11-15 09:49:55 -050039};
40
41const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
42
Lokesh Vutla1f684512015-06-04 16:42:33 +053043void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
44{
45 int i;
46 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
47
48 for (i = 0; i < size; i++, pad++)
49 writel(pad->val, base + pad->offset);
50}
51
Sricharan508a58f2011-11-15 09:49:55 -050052#ifdef CONFIG_SPL_BUILD
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000053/* LPDDR2 specific IO settings */
54static void io_settings_lpddr2(void)
55{
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000056 const struct ctrl_ioregs *ioregs;
57
58 get_ioregs(&ioregs);
59 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
60 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
61 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
63 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
64 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
65 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
66 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
67 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000068}
69
70/* DDR3 specific IO settings */
71static void io_settings_ddr3(void)
72{
73 u32 io_settings = 0;
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000074 const struct ctrl_ioregs *ioregs;
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000075
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000076 get_ioregs(&ioregs);
77 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
78 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
79 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000080
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000081 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
82 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
83 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000084
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000085 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
86 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
Lokesh Vutlaa5c5c5b2015-06-03 14:43:26 +053087
88 if (!is_dra7xx()) {
89 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
90 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
91 }
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000092
93 /* omap5432 does not use lpddr2 */
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000094 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +000095
Lokesh Vutlaef1697e2013-02-04 04:22:05 +000096 writel(ioregs->ctrl_emif_sdram_config_ext,
97 (*ctrl)->control_emif1_sdram_config_ext);
Lokesh Vutlaa5c5c5b2015-06-03 14:43:26 +053098 if (!is_dra72x())
99 writel(ioregs->ctrl_emif_sdram_config_ext,
100 (*ctrl)->control_emif2_sdram_config_ext);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000101
Sricharan R92b04822013-05-30 03:19:39 +0000102 if (is_omap54xx()) {
103 /* Disable DLL select */
104 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000105 & 0xFFEFFFFF);
Sricharan R92b04822013-05-30 03:19:39 +0000106 writel(io_settings,
107 (*ctrl)->control_port_emif1_sdram_config);
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000108
Sricharan R92b04822013-05-30 03:19:39 +0000109 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000110 & 0xFFEFFFFF);
Sricharan R92b04822013-05-30 03:19:39 +0000111 writel(io_settings,
112 (*ctrl)->control_port_emif2_sdram_config);
113 } else {
114 writel(ioregs->ctrl_ddr_ctrl_ext_0,
115 (*ctrl)->control_ddr_control_ext_0);
116 }
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000117}
118
Sricharan508a58f2011-11-15 09:49:55 -0500119/*
120 * Some tuning of IOs for optimal power and performance
121 */
122void do_io_settings(void)
123{
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000124 u32 io_settings = 0, mask = 0;
Tom Rini7c352cd2015-06-05 15:51:11 +0530125 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000126
127 /* Impedance settings EMMC, C2C 1,2, hsi2 */
128 mask = (ds_mask << 2) | (ds_mask << 8) |
129 (ds_mask << 16) | (ds_mask << 18);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000130 io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000131 (~mask);
132 io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
133 (ds_45_ohm << 18) | (ds_60_ohm << 2);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000134 writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000135
136 /* Impedance settings Mcspi2 */
137 mask = (ds_mask << 30);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000138 io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000139 (~mask);
140 io_settings |= (ds_60_ohm << 30);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000141 writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000142
143 /* Impedance settings C2C 3,4 */
144 mask = (ds_mask << 14) | (ds_mask << 16);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000145 io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000146 (~mask);
147 io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000148 writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000149
150 /* Slew rate settings EMMC, C2C 1,2 */
151 mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000152 io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000153 (~mask);
154 io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000155 writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000156
157 /* Slew rate settings hsi2, Mcspi2 */
158 mask = (sc_mask << 24) | (sc_mask << 28);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000159 io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000160 (~mask);
161 io_settings |= (sc_fast << 28) | (sc_fast << 24);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000162 writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000163
164 /* Slew rate settings C2C 3,4 */
165 mask = (sc_mask << 16) | (sc_mask << 18);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000166 io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000167 (~mask);
168 io_settings |= (sc_na << 16) | (sc_na << 18);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000169 writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000170
171 /* impedance and slew rate settings for usb */
172 mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
173 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000174 io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000175 (~mask);
176 io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
177 (ds_60_ohm << 23) | (sc_fast << 20) |
178 (sc_fast << 17) | (sc_fast << 14);
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000179 writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
SRICHARAN R6ad8d672012-03-12 02:25:36 +0000180
Tom Rini7c352cd2015-06-05 15:51:11 +0530181 if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
Lokesh Vutlaeb4e18e2012-05-22 00:03:23 +0000182 io_settings_lpddr2();
183 else
184 io_settings_ddr3();
Sricharan508a58f2011-11-15 09:49:55 -0500185}
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000186
187static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
188 {0x45, 0x1}, /* 12 MHz */
189 {-1, -1}, /* 13 MHz */
190 {0x63, 0x2}, /* 16.8 MHz */
191 {0x57, 0x2}, /* 19.2 MHz */
192 {0x20, 0x1}, /* 26 MHz */
193 {-1, -1}, /* 27 MHz */
194 {0x41, 0x3} /* 38.4 MHz */
195};
196
197void srcomp_enable(void)
198{
199 u32 srcomp_value, mul_factor, div_factor, clk_val, i;
200 u32 sysclk_ind = get_sys_clk_index();
201 u32 omap_rev = omap_revision();
202
Lokesh Vutlae9d6cd02013-05-30 03:19:32 +0000203 if (!is_omap54xx())
204 return;
205
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000206 mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
207 div_factor = srcomp_parameters[sysclk_ind].divide_factor;
208
209 for (i = 0; i < 4; i++) {
210 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
211 srcomp_value &=
212 ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
213 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
214 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
215 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
216 }
217
218 if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
219 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
220 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
221 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
222
223 for (i = 0; i < 4; i++) {
224 srcomp_value =
225 readl((*ctrl)->control_srcomp_north_side + i*4);
226 srcomp_value &= ~PWRDWN_XS_MASK;
227 writel(srcomp_value,
228 (*ctrl)->control_srcomp_north_side + i*4);
229
230 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
231 & SRCODE_READ_XS_MASK) >>
232 SRCODE_READ_XS_SHIFT) == 0)
233 ;
234
235 srcomp_value =
236 readl((*ctrl)->control_srcomp_north_side + i*4);
237 srcomp_value &= ~OVERRIDE_XS_MASK;
238 writel(srcomp_value,
239 (*ctrl)->control_srcomp_north_side + i*4);
240 }
241 } else {
242 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
243 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
244 DIVIDE_FACTOR_XS_MASK);
245 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
246 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
247 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
248
249 for (i = 0; i < 4; i++) {
250 srcomp_value =
251 readl((*ctrl)->control_srcomp_north_side + i*4);
252 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
253 writel(srcomp_value,
254 (*ctrl)->control_srcomp_north_side + i*4);
255
256 srcomp_value =
257 readl((*ctrl)->control_srcomp_north_side + i*4);
258 srcomp_value &= ~OVERRIDE_XS_MASK;
259 writel(srcomp_value,
260 (*ctrl)->control_srcomp_north_side + i*4);
261 }
262
263 srcomp_value =
264 readl((*ctrl)->control_srcomp_east_side_wkup);
265 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
266 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
267
268 srcomp_value =
269 readl((*ctrl)->control_srcomp_east_side_wkup);
270 srcomp_value &= ~OVERRIDE_XS_MASK;
271 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
272
273 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
274 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
275 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
276
277 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
278 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
279 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
280
281 for (i = 0; i < 4; i++) {
282 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
283 & SRCODE_READ_XS_MASK) >>
284 SRCODE_READ_XS_SHIFT) == 0)
285 ;
286
287 srcomp_value =
288 readl((*ctrl)->control_srcomp_north_side + i*4);
289 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
290 writel(srcomp_value,
291 (*ctrl)->control_srcomp_north_side + i*4);
292 }
293
294 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
295 SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
296 ;
297
298 srcomp_value =
299 readl((*ctrl)->control_srcomp_east_side_wkup);
300 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
301 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
302 }
303}
Sricharan508a58f2011-11-15 09:49:55 -0500304#endif
305
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000306void config_data_eye_leveling_samples(u32 emif_base)
307{
SRICHARAN R6c709352013-11-08 17:40:37 +0530308 const struct ctrl_ioregs *ioregs;
309
310 get_ioregs(&ioregs);
311
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000312 /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
313 if (emif_base == EMIF1_BASE)
SRICHARAN R6c709352013-11-08 17:40:37 +0530314 writel(ioregs->ctrl_emif_sdram_config_ext_final,
315 (*ctrl)->control_emif1_sdram_config_ext);
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000316 else if (emif_base == EMIF2_BASE)
SRICHARAN R6c709352013-11-08 17:40:37 +0530317 writel(ioregs->ctrl_emif_sdram_config_ext_final,
318 (*ctrl)->control_emif2_sdram_config_ext);
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000319}
320
Nishanth Menonfc7368e2015-03-09 17:12:07 -0500321void init_cpu_configuration(void)
322{
323 u32 l2actlr;
324
325 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
326 /*
327 * L2ACTLR: Ensure to enable the following:
328 * 3: Disable clean/evict push to external
329 * 4: Disable WriteUnique and WriteLineUnique transactions from master
330 * 8: Disable DVM/CMO message broadcast
331 */
332 l2actlr |= 0x118;
333 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
334}
335
Sricharan508a58f2011-11-15 09:49:55 -0500336void init_omap_revision(void)
337{
338 /*
339 * For some of the ES2/ES1 boards ID_CODE is not reliable:
340 * Also, ES1 and ES2 have different ARM revisions
341 * So use ARM revision for identification
342 */
343 unsigned int rev = cortex_rev();
344
SRICHARAN Reed7c0f2013-02-12 01:33:41 +0000345 switch (readl(CONTROL_ID_CODE)) {
346 case OMAP5430_CONTROL_ID_CODE_ES1_0:
347 *omap_si_rev = OMAP5430_ES1_0;
348 if (rev == MIDR_CORTEX_A15_R2P2)
349 *omap_si_rev = OMAP5430_ES2_0;
350 break;
351 case OMAP5432_CONTROL_ID_CODE_ES1_0:
352 *omap_si_rev = OMAP5432_ES1_0;
353 if (rev == MIDR_CORTEX_A15_R2P2)
354 *omap_si_rev = OMAP5432_ES2_0;
355 break;
356 case OMAP5430_CONTROL_ID_CODE_ES2_0:
357 *omap_si_rev = OMAP5430_ES2_0;
358 break;
359 case OMAP5432_CONTROL_ID_CODE_ES2_0:
360 *omap_si_rev = OMAP5432_ES2_0;
SRICHARAN Rcdd50a82012-03-12 02:25:39 +0000361 break;
Lokesh Vutlade626882013-02-12 21:29:03 +0000362 case DRA752_CONTROL_ID_CODE_ES1_0:
363 *omap_si_rev = DRA752_ES1_0;
364 break;
Nishanth Menon3ac8c0b2014-01-14 10:54:42 -0600365 case DRA752_CONTROL_ID_CODE_ES1_1:
366 *omap_si_rev = DRA752_ES1_1;
367 break;
Lokesh Vutlaee77a232014-05-15 11:08:38 +0530368 case DRA722_CONTROL_ID_CODE_ES1_0:
369 *omap_si_rev = DRA722_ES1_0;
370 break;
Sricharan508a58f2011-11-15 09:49:55 -0500371 default:
SRICHARAN R087189f2012-03-12 02:25:40 +0000372 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
Sricharan508a58f2011-11-15 09:49:55 -0500373 }
Nishanth Menonfc7368e2015-03-09 17:12:07 -0500374 init_cpu_configuration();
Sricharan508a58f2011-11-15 09:49:55 -0500375}
SRICHARAN R06964732012-03-12 02:25:52 +0000376
377void reset_cpu(ulong ignored)
378{
379 u32 omap_rev = omap_revision();
380
381 /*
382 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
383 * So use cold reset in case instead.
384 */
385 if (omap_rev == OMAP5430_ES1_0)
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000386 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
SRICHARAN R06964732012-03-12 02:25:52 +0000387 else
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000388 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
389}
390
391u32 warm_reset(void)
392{
393 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
SRICHARAN R06964732012-03-12 02:25:52 +0000394}
Lokesh Vutla0b1b60c2013-04-17 20:49:40 +0000395
396void setup_warmreset_time(void)
397{
398 u32 rst_time, rst_val;
399
400#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
401 rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
402#else
403 rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
404#endif
405 rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
406
407 if (rst_time > RSTTIME1_MASK)
408 rst_time = RSTTIME1_MASK;
409
410 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
411 rst_val |= rst_time;
412 writel(rst_val, (*prcm)->prm_rsttime);
413}
Praveen Rao5f603762015-03-09 17:12:06 -0500414
415void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
416 u32 cpu_rev_comb, u32 cpu_variant,
417 u32 cpu_rev)
418{
419 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
420}