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wdenkba56f622004-02-06 23:19:44 +00001/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21/*----------------------------------------------------------------------------+
22|
23| File Name: enetemac.h
24|
25| Function: Header file for the EMAC3 macro on the 405GP.
26|
27| Author: Mark Wisner
28|
29| Change Activity-
30|
31| Date Description of Change BY
32| --------- --------------------- ---
33| 29-Apr-99 Created MKW
34|
35+----------------------------------------------------------------------------*/
36/*----------------------------------------------------------------------------+
37| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
38| ported to handle 440GP and 440GX multiple EMACs
39+----------------------------------------------------------------------------*/
40
Stefan Roesed6c61aa2005-08-16 18:18:00 +020041#ifndef _PPC4XX_ENET_H_
42#define _PPC4XX_ENET_H_
wdenkba56f622004-02-06 23:19:44 +000043
wdenkba56f622004-02-06 23:19:44 +000044#include <net.h>
45#include "405_mal.h"
46
47
48/*-----------------------------------------------------------------------------+
49| General enternet defines. 802 frames are not supported.
50+-----------------------------------------------------------------------------*/
51#define ENET_ADDR_LENGTH 6
52#define ENET_ARPTYPE 0x806
53#define ARP_REQUEST 1
54#define ARP_REPLY 2
55#define ENET_IPTYPE 0x800
56#define ARP_CACHE_SIZE 5
57
58#define NUM_TX_BUFF 1
59#define NUM_RX_BUFF PKTBUFSRX
60
61struct enet_frame {
62 unsigned char dest_addr[ENET_ADDR_LENGTH];
63 unsigned char source_addr[ENET_ADDR_LENGTH];
64 unsigned short type;
65 unsigned char enet_data[1];
66};
67
68struct arp_entry {
69 unsigned long inet_address;
70 unsigned char mac_address[ENET_ADDR_LENGTH];
71 unsigned long valid;
72 unsigned long sec;
73 unsigned long nsec;
74};
75
76
77/* Statistic Areas */
78#define MAX_ERR_LOG 10
79
80typedef struct emac_stats_st{ /* Statistic Block */
81 int data_len_err;
82 int rx_frames;
83 int rx;
84 int rx_prot_err;
85 int int_err;
Stefan Roesed6c61aa2005-08-16 18:18:00 +020086 int pkts_tx;
87 int pkts_rx;
88 int pkts_handled;
wdenkba56f622004-02-06 23:19:44 +000089 short tx_err_log[MAX_ERR_LOG];
90 short rx_err_log[MAX_ERR_LOG];
91} EMAC_STATS_ST, *EMAC_STATS_PST;
92
Stefan Roesed6c61aa2005-08-16 18:18:00 +020093/* Structure containing variables used by the shared code (4xx_enet.c) */
94typedef struct emac_4xx_hw_st {
wdenkba56f622004-02-06 23:19:44 +000095 uint32_t hw_addr; /* EMAC offset */
96 uint32_t tah_addr; /* TAH offset */
97 uint32_t phy_id;
98 uint32_t phy_addr;
99 uint32_t original_fc;
100 uint32_t txcw;
101 uint32_t autoneg_failed;
102 uint32_t emac_ier;
103 volatile mal_desc_t *tx;
104 volatile mal_desc_t *rx;
105 bd_t *bis; /* for eth_init upon mal error */
106 mal_desc_t *alloc_tx_buf;
107 mal_desc_t *alloc_rx_buf;
108 char *txbuf_ptr;
109 uint16_t devnum;
110 int get_link_status;
111 int tbi_compatibility_en;
112 int tbi_compatibility_on;
113 int fc_send_xon;
114 int report_tx_early;
115 int first_init;
116 int tx_err_index;
117 int rx_err_index;
118 int rx_slot; /* MAL Receive Slot */
119 int rx_i_index; /* Receive Interrupt Queue Index */
120 int rx_u_index; /* Receive User Queue Index */
121 int tx_slot; /* MAL Transmit Slot */
122 int tx_i_index; /* Transmit Interrupt Queue Index */
123 int tx_u_index; /* Transmit User Queue Index */
124 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
125 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
126 int is_receiving; /* sync with eth interrupt */
127 int print_speed; /* print speed message upon start */
128 EMAC_STATS_ST stats;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200129} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
wdenkba56f622004-02-06 23:19:44 +0000130
131
Stefan Roese846b0dd2005-08-08 12:42:22 +0200132#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +0000133#define EMAC_NUM_DEV 4
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100134#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
135 defined(CONFIG_NET_MULTI) && \
136 !defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +0000137#define EMAC_NUM_DEV 2
138#else
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200139#define EMAC_NUM_DEV 1
wdenkba56f622004-02-06 23:19:44 +0000140#endif
141
142
143/*ZMII Bridge Register addresses */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200144#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200145#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
146#else
wdenkba56f622004-02-06 23:19:44 +0000147#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200148#endif
wdenkba56f622004-02-06 23:19:44 +0000149#define ZMII_FER (ZMII_BASE)
150#define ZMII_SSR (ZMII_BASE + 4)
151#define ZMII_SMIISR (ZMII_BASE + 8)
152
153#define ZMII_RMII 0x22000000
154#define ZMII_MDI0 0x80000000
155
156/* ZMII FER Register Bit Definitions */
157#define ZMII_FER_MDI (0x8)
158#define ZMII_FER_SMII (0x4)
159#define ZMII_FER_RMII (0x2)
160#define ZMII_FER_MII (0x1)
161
162#define ZMII_FER_RSVD11 (0x00200000)
163#define ZMII_FER_RSVD10 (0x00100000)
164#define ZMII_FER_RSVD14_31 (0x0003FFFF)
165
166#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
167
168
169/* ZMII Speed Selection Register Bit Definitions */
170#define ZMII_SSR_SCI (0x4)
171#define ZMII_SSR_FSS (0x2)
172#define ZMII_SSR_SP (0x1)
173#define ZMII_SSR_RSVD16_31 (0x0000FFFF)
174
175#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16)
176
177
178/* ZMII SMII Status Register Bit Definitions */
179#define ZMII_SMIISR_E1 (0x80)
180#define ZMII_SMIISR_EC (0x40)
181#define ZMII_SMIISR_EN (0x20)
182#define ZMII_SMIISR_EJ (0x10)
183#define ZMII_SMIISR_EL (0x08)
184#define ZMII_SMIISR_ED (0x04)
185#define ZMII_SMIISR_ES (0x02)
186#define ZMII_SMIISR_EF (0x01)
187
188#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
189
190/* RGMII Register Addresses */
191#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
192#define RGMII_FER (RGMII_BASE + 0x00)
193#define RGMII_SSR (RGMII_BASE + 0x04)
194
195/* RGMII Function Enable (FER) Register Bit Definitions */
196/* Note: for EMAC 2 and 3 only, 440GX only */
197#define RGMII_FER_DIS (0x00)
198#define RGMII_FER_RTBI (0x04)
199#define RGMII_FER_RGMII (0x05)
200#define RGMII_FER_TBI (0x06)
201#define RGMII_FER_GMII (0x07)
202
203#define RGMII_FER_V(__x) ((__x - 2) * 4)
204
205/* RGMII Speed Selection Register Bit Definitions */
206#define RGMII_SSR_SP_10MBPS (0x00)
207#define RGMII_SSR_SP_100MBPS (0x02)
208#define RGMII_SSR_SP_1000MBPS (0x04)
209
210#define RGMII_SSR_V(__x) ((__x -2) * 8)
211
212
213/*---------------------------------------------------------------------------+
214| TCP/IP Acceleration Hardware (TAH) 440GX Only
215+---------------------------------------------------------------------------*/
Stefan Roese846b0dd2005-08-08 12:42:22 +0200216#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +0000217#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
218#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
219#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
220#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
221#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
222#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
223#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
224#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
225#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
226#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
227
wdenkba56f622004-02-06 23:19:44 +0000228/* TAH Revision */
229#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
230#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
231
232#define TAH_REV_RN_V (8)
233#define TAH_REV_BN_V (0)
234
235/* TAH Mode Register */
236#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
237#define TAH_MR_SR (0x40000000) /* Software reset */
238#define TAH_MR_ST (0x3F000000) /* Send Threshold */
239#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
240#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
241#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
242#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
243
244#define TAH_MR_ST_V (20)
245#define TAH_MR_TFS_V (17)
246
247#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
248#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
249#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
250#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
251#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
252
253
254/* TAH Segment Size Registers 0:5 */
255#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
256#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
257#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
258
259/* TAH Transmit Status Register */
260#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
261#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
262#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
263#define TAH_TSR_IPOP (0x10000000) /* IP option present */
264#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
265#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
266#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
267#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
268#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
269#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
270#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
271#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
272#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
273#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
274#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200275#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000276
277
278/* Ethernet MAC Regsiter Addresses */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200279#if defined(CONFIG_440)
Stefan Roese846b0dd2005-08-08 12:42:22 +0200280#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200281#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
282#else
wdenkba56f622004-02-06 23:19:44 +0000283#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200284#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200285#else
286#define EMAC_BASE 0xEF600800
287#endif
wdenkba56f622004-02-06 23:19:44 +0000288
289#define EMAC_M0 (EMAC_BASE)
290#define EMAC_M1 (EMAC_BASE + 4)
291#define EMAC_TXM0 (EMAC_BASE + 8)
292#define EMAC_TXM1 (EMAC_BASE + 12)
293#define EMAC_RXM (EMAC_BASE + 16)
294#define EMAC_ISR (EMAC_BASE + 20)
295#define EMAC_IER (EMAC_BASE + 24)
296#define EMAC_IAH (EMAC_BASE + 28)
297#define EMAC_IAL (EMAC_BASE + 32)
298#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
299#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
300#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
301#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
302#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
303#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
304#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
305#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
306#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
307#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
308#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
309#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
310#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
311#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
312#define EMAC_STACR (EMAC_BASE + 92)
313#define EMAC_TRTR (EMAC_BASE + 96)
314#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
315
316/* bit definitions */
317/* MODE REG 0 */
318#define EMAC_M0_RXI (0x80000000)
319#define EMAC_M0_TXI (0x40000000)
320#define EMAC_M0_SRST (0x20000000)
321#define EMAC_M0_TXE (0x10000000)
322#define EMAC_M0_RXE (0x08000000)
323#define EMAC_M0_WKE (0x04000000)
324
Stefan Roese17f50f222005-08-04 17:09:16 +0200325/* on 440GX EMAC_MR1 has a different layout! */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100326#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +0000327/* MODE Reg 1 */
328#define EMAC_M1_FDE (0x80000000)
329#define EMAC_M1_ILE (0x40000000)
330#define EMAC_M1_VLE (0x20000000)
331#define EMAC_M1_EIFC (0x10000000)
332#define EMAC_M1_APP (0x08000000)
333#define EMAC_M1_RSVD (0x06000000)
334#define EMAC_M1_IST (0x01000000)
335#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
336#define EMAC_M1_MF_100MBPS (0x00400000)
337#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
338#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
339#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
340#define EMAC_M1_RFS_2K (0x00100000)
341#define EMAC_M1_RFS_1K (0x00080000)
342#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
343#define EMAC_M1_TX_FIFO_8K (0x00040000)
344#define EMAC_M1_TX_FIFO_4K (0x00030000)
345#define EMAC_M1_TX_FIFO_2K (0x00020000)
346#define EMAC_M1_TX_FIFO_1K (0x00010000)
347#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
348#define EMAC_M1_MWSW (0x00007000)
349#define EMAC_M1_JUMBO_ENABLE (0x00000800)
350#define EMAC_M1_IPPA (0x000007c0)
351#define EMAC_M1_OBCI_GT100 (0x00000020)
352#define EMAC_M1_OBCI_100 (0x00000018)
353#define EMAC_M1_OBCI_83 (0x00000010)
354#define EMAC_M1_OBCI_66 (0x00000008)
355#define EMAC_M1_RSVD1 (0x00000007)
Stefan Roese846b0dd2005-08-08 12:42:22 +0200356#else /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200357/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
358#define EMAC_M1_FDE 0x80000000
359#define EMAC_M1_ILE 0x40000000
360#define EMAC_M1_VLE 0x20000000
361#define EMAC_M1_EIFC 0x10000000
362#define EMAC_M1_APP 0x08000000
363#define EMAC_M1_AEMI 0x02000000
364#define EMAC_M1_IST 0x01000000
365#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
366#define EMAC_M1_MF_100MBPS 0x00400000
367#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
368#define EMAC_M1_RFS_2K 0x00200000
369#define EMAC_M1_RFS_1K 0x00100000
370#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
371#define EMAC_M1_TX_FIFO_1K 0x00040000
372#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
373#define EMAC_M1_TR0_MULTI 0x00008000
374#define EMAC_M1_TR1_DEPEND 0x00004000
375#define EMAC_M1_TR1_MULTI 0x00002000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200376#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roese17f50f222005-08-04 17:09:16 +0200377#define EMAC_M1_JUMBO_ENABLE 0x00001000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200378#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
379#endif /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200380
wdenkba56f622004-02-06 23:19:44 +0000381/* Transmit Mode Register 0 */
382#define EMAC_TXM0_GNP0 (0x80000000)
383#define EMAC_TXM0_GNP1 (0x40000000)
384#define EMAC_TXM0_GNPD (0x20000000)
385#define EMAC_TXM0_FC (0x10000000)
386
387/* Receive Mode Register */
388#define EMAC_RMR_SP (0x80000000)
389#define EMAC_RMR_SFCS (0x40000000)
390#define EMAC_RMR_ARRP (0x20000000)
391#define EMAC_RMR_ARP (0x10000000)
392#define EMAC_RMR_AROP (0x08000000)
393#define EMAC_RMR_ARPI (0x04000000)
394#define EMAC_RMR_PPP (0x02000000)
395#define EMAC_RMR_PME (0x01000000)
396#define EMAC_RMR_PMME (0x00800000)
397#define EMAC_RMR_IAE (0x00400000)
398#define EMAC_RMR_MIAE (0x00200000)
399#define EMAC_RMR_BAE (0x00100000)
400#define EMAC_RMR_MAE (0x00080000)
401
402/* Interrupt Status & enable Regs */
403#define EMAC_ISR_OVR (0x02000000)
404#define EMAC_ISR_PP (0x01000000)
405#define EMAC_ISR_BP (0x00800000)
406#define EMAC_ISR_RP (0x00400000)
407#define EMAC_ISR_SE (0x00200000)
408#define EMAC_ISR_SYE (0x00100000)
409#define EMAC_ISR_BFCS (0x00080000)
410#define EMAC_ISR_PTLE (0x00040000)
411#define EMAC_ISR_ORE (0x00020000)
412#define EMAC_ISR_IRE (0x00010000)
413#define EMAC_ISR_DBDM (0x00000200)
414#define EMAC_ISR_DB0 (0x00000100)
415#define EMAC_ISR_SE0 (0x00000080)
416#define EMAC_ISR_TE0 (0x00000040)
417#define EMAC_ISR_DB1 (0x00000020)
418#define EMAC_ISR_SE1 (0x00000010)
419#define EMAC_ISR_TE1 (0x00000008)
420#define EMAC_ISR_MOS (0x00000002)
421#define EMAC_ISR_MOF (0x00000001)
422
423
424/* STA CONTROL REG */
425#define EMAC_STACR_OC (0x00008000)
426#define EMAC_STACR_PHYE (0x00004000)
427#define EMAC_STACR_WRITE (0x00002000)
428#define EMAC_STACR_READ (0x00001000)
429#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
430#define EMAC_STACR_CLK_66MHZ (0x00000400)
431#define EMAC_STACR_CLK_100MHZ (0x00000C00)
432
433/* Transmit Request Threshold Register */
434#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
435#define EMAC_TRTR_192 (0x10000000)
436#define EMAC_TRTR_128 (0x01000000)
437
438/* the follwing defines are for the MadMAL status and control registers. */
439/* For bits 0..5 look at the mal.h file */
440#define EMAC_TX_CTRL_GFCS (0x0200)
441#define EMAC_TX_CTRL_GP (0x0100)
442#define EMAC_TX_CTRL_ISA (0x0080)
443#define EMAC_TX_CTRL_RSA (0x0040)
444#define EMAC_TX_CTRL_IVT (0x0020)
445#define EMAC_TX_CTRL_RVT (0x0010)
446
447#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
448
449#define EMAC_TX_ST_BFCS (0x0200)
450#define EMAC_TX_ST_BPP (0x0100)
451#define EMAC_TX_ST_LCS (0x0080)
452#define EMAC_TX_ST_ED (0x0040)
453#define EMAC_TX_ST_EC (0x0020)
454#define EMAC_TX_ST_LC (0x0010)
455#define EMAC_TX_ST_MC (0x0008)
456#define EMAC_TX_ST_SC (0x0004)
457#define EMAC_TX_ST_UR (0x0002)
458#define EMAC_TX_ST_SQE (0x0001)
459
460#define EMAC_TX_ST_DEFAULT (0x03F3)
461
462
463/* madmal receive status / Control bits */
464
465#define EMAC_RX_ST_OE (0x0200)
466#define EMAC_RX_ST_PP (0x0100)
467#define EMAC_RX_ST_BP (0x0080)
468#define EMAC_RX_ST_RP (0x0040)
469#define EMAC_RX_ST_SE (0x0020)
470#define EMAC_RX_ST_AE (0x0010)
471#define EMAC_RX_ST_BFCS (0x0008)
472#define EMAC_RX_ST_PTL (0x0004)
473#define EMAC_RX_ST_ORE (0x0002)
474#define EMAC_RX_ST_IRE (0x0001)
475/* all the errors we care about */
476#define EMAC_RX_ERRORS (0x03FF)
477
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200478#endif /* _PPC4XX_ENET_H_ */