| Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __LS1012ARDB_H__ |
| 8 | #define __LS1012ARDB_H__ |
| 9 | |
| 10 | #include "ls1012a_common.h" |
| 11 | |
| 12 | |
| 13 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 14 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
| 15 | #define CONFIG_NR_DRAM_BANKS 2 |
| 16 | #define CONFIG_SYS_SDRAM_SIZE 0x40000000 |
| 17 | |
| 18 | #define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 |
| 19 | #define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 |
| 20 | |
| 21 | #define CONFIG_CMD_MEMINFO |
| 22 | #define CONFIG_CMD_MEMTEST |
| 23 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 24 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| 25 | |
| 26 | /* |
| 27 | * USB |
| 28 | */ |
| 29 | #define CONFIG_HAS_FSL_XHCI_USB |
| 30 | |
| 31 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
| Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame] | 32 | #define CONFIG_USB_XHCI_FSL |
| Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame] | 33 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 34 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame] | 35 | #endif |
| 36 | |
| 37 | /* |
| 38 | * I2C IO expander |
| 39 | */ |
| 40 | |
| 41 | #define I2C_MUX_IO1_ADDR 0x24 |
| 42 | #define __SW_BOOT_MASK 0xFC |
| 43 | #define __SW_BOOT_EMU 0x10 |
| 44 | #define __SW_BOOT_BANK1 0x00 |
| 45 | #define __SW_BOOT_BANK2 0x01 |
| 46 | #define __SW_REV_MASK 0x07 |
| 47 | #define __SW_REV_A 0xF8 |
| 48 | #define __SW_REV_B 0xF0 |
| 49 | |
| 50 | /* MMC */ |
| 51 | #define CONFIG_MMC |
| 52 | #ifdef CONFIG_MMC |
| 53 | #define CONFIG_FSL_ESDHC |
| 54 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 55 | #define CONFIG_GENERIC_MMC |
| 56 | #define CONFIG_DOS_PARTITION |
| 57 | #endif |
| 58 | |
| 59 | /* SATA */ |
| 60 | #define CONFIG_LIBATA |
| 61 | #define CONFIG_SCSI |
| 62 | #define CONFIG_SCSI_AHCI |
| 63 | #define CONFIG_SCSI_AHCI_PLAT |
| 64 | #define CONFIG_CMD_SCSI |
| 65 | #define CONFIG_DOS_PARTITION |
| 66 | #define CONFIG_BOARD_LATE_INIT |
| 67 | |
| 68 | #define CONFIG_SYS_SATA AHCI_BASE_ADDR |
| 69 | |
| 70 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
| 71 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 72 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 73 | CONFIG_SYS_SCSI_MAX_LUN) |
| 74 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
| 75 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 76 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 77 | #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" |
| 78 | |
| 79 | #define CONFIG_SYS_PCI_64BIT |
| 80 | |
| 81 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
| 82 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
| 83 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
| 84 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
| 85 | |
| 86 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
| 87 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
| 88 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
| 89 | |
| 90 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 |
| 91 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 |
| 92 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ |
| 93 | |
| 94 | #define CONFIG_NET_MULTI |
| 95 | #define CONFIG_PCI_PNP |
| 96 | #define CONFIG_PCI_SCAN_SHOW |
| 97 | #define CONFIG_CMD_PCI |
| 98 | |
| 99 | #define CONFIG_CMD_MEMINFO |
| 100 | #define CONFIG_CMD_MEMTEST |
| 101 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 102 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| 103 | |
| 104 | #endif /* __LS1012ARDB_H__ */ |