Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
| 6 | * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> |
| 7 | * |
| 8 | * Based on SPL code from Solidrun tree, which is: |
| 9 | * Author: Tungyi Lin <tungyilin1127@gmail.com> |
| 10 | * |
| 11 | * Derived from EDM_CF_IMX6 code by TechNexion,Inc |
| 12 | * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com> |
| 13 | * |
| 14 | * SPDX-License-Identifier: GPL-2.0+ |
| 15 | */ |
| 16 | |
| 17 | #include <asm/arch/clock.h> |
| 18 | #include <asm/arch/imx-regs.h> |
| 19 | #include <asm/arch/iomux.h> |
| 20 | #include <asm/arch/mx6-pins.h> |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 21 | #include <asm/arch/mxc_hdmi.h> |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 22 | #include <asm/errno.h> |
| 23 | #include <asm/gpio.h> |
| 24 | #include <asm/imx-common/iomux-v3.h> |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 25 | #include <asm/imx-common/video.h> |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 26 | #include <mmc.h> |
| 27 | #include <fsl_esdhc.h> |
Fabio Estevam | 712be3e | 2015-05-04 11:22:55 -0300 | [diff] [blame] | 28 | #include <malloc.h> |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 29 | #include <miiphy.h> |
| 30 | #include <netdev.h> |
| 31 | #include <asm/arch/crm_regs.h> |
| 32 | #include <asm/io.h> |
| 33 | #include <asm/arch/sys_proto.h> |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 34 | #include <spl.h> |
Fabio Estevam | e1d7437 | 2015-04-29 22:28:10 -0300 | [diff] [blame] | 35 | #include <usb.h> |
| 36 | #include <usb/ehci-fsl.h> |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 37 | |
| 38 | DECLARE_GLOBAL_DATA_PTR; |
| 39 | |
| 40 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 41 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 42 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 43 | |
| 44 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| 45 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 46 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 47 | |
| 48 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 49 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 50 | |
| 51 | #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ |
| 52 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 53 | |
| 54 | #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ |
| 55 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 56 | |
| 57 | #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) |
Fabio Estevam | e1d7437 | 2015-04-29 22:28:10 -0300 | [diff] [blame] | 58 | #define USB_H1_VBUS IMX_GPIO_NR(1, 0) |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 59 | |
| 60 | int dram_init(void) |
| 61 | { |
| 62 | gd->ram_size = imx_ddr_size(); |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static iomux_v3_cfg_t const uart1_pads[] = { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 67 | IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
| 68 | IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 72 | IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| 73 | IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| 74 | IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| 75 | IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| 76 | IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| 77 | IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 78 | }; |
| 79 | |
Fabio Estevam | feb6cc5 | 2015-04-25 18:47:19 -0300 | [diff] [blame] | 80 | static iomux_v3_cfg_t const hb_cbi_sense[] = { |
| 81 | /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ |
| 82 | IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), |
| 83 | IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), |
| 84 | }; |
| 85 | |
Fabio Estevam | e1d7437 | 2015-04-29 22:28:10 -0300 | [diff] [blame] | 86 | static iomux_v3_cfg_t const usb_pads[] = { |
| 87 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
| 88 | }; |
| 89 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 90 | static void setup_iomux_uart(void) |
| 91 | { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 92 | SETUP_IOMUX_PADS(uart1_pads); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| 96 | {USDHC2_BASE_ADDR}, |
| 97 | }; |
| 98 | |
| 99 | int board_mmc_getcd(struct mmc *mmc) |
| 100 | { |
| 101 | return 1; /* uSDHC2 is always present */ |
| 102 | } |
| 103 | |
| 104 | int board_mmc_init(bd_t *bis) |
| 105 | { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 106 | SETUP_IOMUX_PADS(usdhc2_pads); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 107 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| 108 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 109 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 110 | |
| 111 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 112 | } |
| 113 | |
| 114 | static iomux_v3_cfg_t const enet_pads[] = { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 115 | IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 116 | IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 117 | /* AR8035 reset */ |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 118 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 119 | /* AR8035 interrupt */ |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 120 | IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 121 | /* GPIO16 -> AR8035 25MHz */ |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 122 | IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), |
| 123 | IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), |
| 124 | IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 125 | IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 126 | IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 127 | IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 128 | IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 129 | /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 130 | IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), |
| 131 | IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 132 | IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
| 133 | IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
| 134 | IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 135 | IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
| 136 | IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
Fabio Estevam | a4d4503 | 2015-05-04 11:22:56 -0300 | [diff] [blame] | 137 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
| 138 | IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | static void setup_iomux_enet(void) |
| 142 | { |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 143 | SETUP_IOMUX_PADS(enet_pads); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 144 | |
| 145 | gpio_direction_output(ETH_PHY_RESET, 0); |
| 146 | mdelay(2); |
| 147 | gpio_set_value(ETH_PHY_RESET, 1); |
| 148 | } |
| 149 | |
| 150 | int board_phy_config(struct phy_device *phydev) |
| 151 | { |
| 152 | if (phydev->drv->config) |
| 153 | phydev->drv->config(phydev); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
Fabio Estevam | 712be3e | 2015-05-04 11:22:55 -0300 | [diff] [blame] | 158 | /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ |
| 159 | #define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) |
| 160 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 161 | int board_eth_init(bd_t *bis) |
| 162 | { |
| 163 | struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
Fabio Estevam | 712be3e | 2015-05-04 11:22:55 -0300 | [diff] [blame] | 164 | struct mii_dev *bus; |
| 165 | struct phy_device *phydev; |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 166 | |
Peng Fan | 6d97dc1 | 2015-08-12 17:46:50 +0800 | [diff] [blame^] | 167 | int ret = enable_fec_anatop_clock(0, ENET_25MHZ); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 168 | if (ret) |
| 169 | return ret; |
| 170 | |
| 171 | /* set gpr1[ENET_CLK_SEL] */ |
| 172 | setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); |
| 173 | |
| 174 | setup_iomux_enet(); |
| 175 | |
Fabio Estevam | 712be3e | 2015-05-04 11:22:55 -0300 | [diff] [blame] | 176 | bus = fec_get_miibus(IMX_FEC_BASE, -1); |
| 177 | if (!bus) |
| 178 | return -EINVAL; |
| 179 | |
| 180 | phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); |
| 181 | if (!phydev) { |
| 182 | ret = -EINVAL; |
| 183 | goto free_bus; |
| 184 | } |
| 185 | |
| 186 | debug("using phy at address %d\n", phydev->addr); |
| 187 | ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); |
| 188 | if (ret) |
| 189 | goto free_phydev; |
| 190 | |
| 191 | return 0; |
| 192 | |
| 193 | free_phydev: |
| 194 | free(phydev); |
| 195 | free_bus: |
| 196 | free(bus); |
| 197 | return ret; |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 198 | } |
| 199 | |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 200 | #ifdef CONFIG_VIDEO_IPUV3 |
| 201 | static void do_enable_hdmi(struct display_info_t const *dev) |
| 202 | { |
| 203 | imx_enable_hdmi_phy(); |
| 204 | } |
| 205 | |
| 206 | struct display_info_t const displays[] = { |
| 207 | { |
| 208 | .bus = -1, |
| 209 | .addr = 0, |
| 210 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 211 | .detect = detect_hdmi, |
| 212 | .enable = do_enable_hdmi, |
| 213 | .mode = { |
| 214 | .name = "HDMI", |
| 215 | /* 1024x768@60Hz (VESA)*/ |
| 216 | .refresh = 60, |
| 217 | .xres = 1024, |
| 218 | .yres = 768, |
| 219 | .pixclock = 15384, |
| 220 | .left_margin = 160, |
| 221 | .right_margin = 24, |
| 222 | .upper_margin = 29, |
| 223 | .lower_margin = 3, |
| 224 | .hsync_len = 136, |
| 225 | .vsync_len = 6, |
| 226 | .sync = FB_SYNC_EXT, |
| 227 | .vmode = FB_VMODE_NONINTERLACED |
| 228 | } |
| 229 | } |
| 230 | }; |
| 231 | |
| 232 | size_t display_count = ARRAY_SIZE(displays); |
| 233 | |
| 234 | static int setup_display(void) |
| 235 | { |
| 236 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 237 | int reg; |
| 238 | int timeout = 100000; |
| 239 | |
| 240 | enable_ipu_clock(); |
| 241 | imx_setup_hdmi(); |
| 242 | |
| 243 | /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ |
| 244 | setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); |
| 245 | |
| 246 | reg = readl(&ccm->analog_pll_video); |
| 247 | reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; |
| 248 | reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); |
| 249 | reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; |
| 250 | reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); |
| 251 | writel(reg, &ccm->analog_pll_video); |
| 252 | |
| 253 | writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); |
| 254 | writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); |
| 255 | |
| 256 | reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; |
| 257 | writel(reg, &ccm->analog_pll_video); |
| 258 | |
| 259 | while (timeout--) |
| 260 | if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) |
| 261 | break; |
| 262 | if (timeout < 0) { |
| 263 | printf("Warning: video pll lock timeout!\n"); |
| 264 | return -ETIMEDOUT; |
| 265 | } |
| 266 | |
| 267 | reg = readl(&ccm->analog_pll_video); |
| 268 | reg |= BM_ANADIG_PLL_VIDEO_ENABLE; |
| 269 | reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; |
| 270 | writel(reg, &ccm->analog_pll_video); |
| 271 | |
| 272 | /* gate ipu1_di0_clk */ |
| 273 | clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); |
| 274 | |
| 275 | /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ |
| 276 | reg = readl(&ccm->chsccdr); |
| 277 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | |
| 278 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | |
| 279 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
| 280 | reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | |
| 281 | (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | |
| 282 | (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| 283 | writel(reg, &ccm->chsccdr); |
| 284 | |
| 285 | /* enable ipu1_di0_clk */ |
| 286 | setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | #endif /* CONFIG_VIDEO_IPUV3 */ |
| 291 | |
Fabio Estevam | e1d7437 | 2015-04-29 22:28:10 -0300 | [diff] [blame] | 292 | #ifdef CONFIG_USB_EHCI_MX6 |
| 293 | static void setup_usb(void) |
| 294 | { |
| 295 | SETUP_IOMUX_PADS(usb_pads); |
| 296 | } |
| 297 | |
| 298 | int board_ehci_hcd_init(int port) |
| 299 | { |
| 300 | if (port == 1) |
| 301 | gpio_direction_output(USB_H1_VBUS, 1); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | #endif |
| 306 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 307 | int board_early_init_f(void) |
| 308 | { |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 309 | int ret = 0; |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 310 | setup_iomux_uart(); |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 311 | |
| 312 | #ifdef CONFIG_VIDEO_IPUV3 |
| 313 | ret = setup_display(); |
| 314 | #endif |
Fabio Estevam | e1d7437 | 2015-04-29 22:28:10 -0300 | [diff] [blame] | 315 | |
| 316 | #ifdef CONFIG_USB_EHCI_MX6 |
| 317 | setup_usb(); |
| 318 | #endif |
Fabio Estevam | f68a9c6 | 2015-04-29 22:28:09 -0300 | [diff] [blame] | 319 | return ret; |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 320 | } |
| 321 | |
| 322 | int board_init(void) |
| 323 | { |
| 324 | /* address of boot parameters */ |
| 325 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 326 | |
| 327 | return 0; |
| 328 | } |
| 329 | |
Fabio Estevam | feb6cc5 | 2015-04-25 18:47:19 -0300 | [diff] [blame] | 330 | static bool is_hummingboard(void) |
| 331 | { |
| 332 | int val1, val2; |
| 333 | |
| 334 | SETUP_IOMUX_PADS(hb_cbi_sense); |
| 335 | |
| 336 | gpio_direction_input(IMX_GPIO_NR(4, 9)); |
| 337 | gpio_direction_input(IMX_GPIO_NR(3, 4)); |
| 338 | |
| 339 | val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); |
| 340 | val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); |
| 341 | |
| 342 | /* |
| 343 | * Machine selection - |
| 344 | * Machine val1, val2 |
| 345 | * ------------------------- |
| 346 | * HB rev 3.x x 0 |
| 347 | * CBi 0 1 |
| 348 | * HB 1 1 |
| 349 | */ |
| 350 | |
| 351 | if (val2 == 0) |
| 352 | return true; |
| 353 | else if (val1 == 0) |
| 354 | return false; |
| 355 | else |
| 356 | return true; |
| 357 | } |
| 358 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 359 | int checkboard(void) |
| 360 | { |
Fabio Estevam | feb6cc5 | 2015-04-25 18:47:19 -0300 | [diff] [blame] | 361 | if (is_hummingboard()) |
| 362 | puts("Board: MX6 Hummingboard\n"); |
| 363 | else |
| 364 | puts("Board: MX6 Cubox-i\n"); |
| 365 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 366 | return 0; |
| 367 | } |
| 368 | |
Fabio Estevam | 205d586 | 2015-04-25 18:47:21 -0300 | [diff] [blame] | 369 | static bool is_mx6q(void) |
| 370 | { |
| 371 | if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) |
| 372 | return true; |
| 373 | else |
| 374 | return false; |
| 375 | } |
| 376 | |
| 377 | int board_late_init(void) |
| 378 | { |
| 379 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 380 | if (is_hummingboard()) |
| 381 | setenv("board_name", "HUMMINGBOARD"); |
| 382 | else |
| 383 | setenv("board_name", "CUBOXI"); |
| 384 | |
| 385 | if (is_mx6q()) |
| 386 | setenv("board_rev", "MX6Q"); |
| 387 | else |
| 388 | setenv("board_rev", "MX6DL"); |
| 389 | #endif |
| 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 394 | #ifdef CONFIG_SPL_BUILD |
Fabio Estevam | cfdcc5f | 2015-04-25 18:47:17 -0300 | [diff] [blame] | 395 | #include <asm/arch/mx6-ddr.h> |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 396 | static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 397 | .dram_sdclk_0 = 0x00020030, |
| 398 | .dram_sdclk_1 = 0x00020030, |
| 399 | .dram_cas = 0x00020030, |
| 400 | .dram_ras = 0x00020030, |
| 401 | .dram_reset = 0x00020030, |
| 402 | .dram_sdcke0 = 0x00003000, |
| 403 | .dram_sdcke1 = 0x00003000, |
| 404 | .dram_sdba2 = 0x00000000, |
| 405 | .dram_sdodt0 = 0x00003030, |
| 406 | .dram_sdodt1 = 0x00003030, |
| 407 | .dram_sdqs0 = 0x00000030, |
| 408 | .dram_sdqs1 = 0x00000030, |
| 409 | .dram_sdqs2 = 0x00000030, |
| 410 | .dram_sdqs3 = 0x00000030, |
| 411 | .dram_sdqs4 = 0x00000030, |
| 412 | .dram_sdqs5 = 0x00000030, |
| 413 | .dram_sdqs6 = 0x00000030, |
| 414 | .dram_sdqs7 = 0x00000030, |
| 415 | .dram_dqm0 = 0x00020030, |
| 416 | .dram_dqm1 = 0x00020030, |
| 417 | .dram_dqm2 = 0x00020030, |
| 418 | .dram_dqm3 = 0x00020030, |
| 419 | .dram_dqm4 = 0x00020030, |
| 420 | .dram_dqm5 = 0x00020030, |
| 421 | .dram_dqm6 = 0x00020030, |
| 422 | .dram_dqm7 = 0x00020030, |
| 423 | }; |
| 424 | |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 425 | static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { |
| 426 | .dram_sdclk_0 = 0x00000028, |
| 427 | .dram_sdclk_1 = 0x00000028, |
| 428 | .dram_cas = 0x00000028, |
| 429 | .dram_ras = 0x00000028, |
| 430 | .dram_reset = 0x000c0028, |
| 431 | .dram_sdcke0 = 0x00003000, |
| 432 | .dram_sdcke1 = 0x00003000, |
| 433 | .dram_sdba2 = 0x00000000, |
| 434 | .dram_sdodt0 = 0x00003030, |
| 435 | .dram_sdodt1 = 0x00003030, |
| 436 | .dram_sdqs0 = 0x00000028, |
| 437 | .dram_sdqs1 = 0x00000028, |
| 438 | .dram_sdqs2 = 0x00000028, |
| 439 | .dram_sdqs3 = 0x00000028, |
| 440 | .dram_sdqs4 = 0x00000028, |
| 441 | .dram_sdqs5 = 0x00000028, |
| 442 | .dram_sdqs6 = 0x00000028, |
| 443 | .dram_sdqs7 = 0x00000028, |
| 444 | .dram_dqm0 = 0x00000028, |
| 445 | .dram_dqm1 = 0x00000028, |
| 446 | .dram_dqm2 = 0x00000028, |
| 447 | .dram_dqm3 = 0x00000028, |
| 448 | .dram_dqm4 = 0x00000028, |
| 449 | .dram_dqm5 = 0x00000028, |
| 450 | .dram_dqm6 = 0x00000028, |
| 451 | .dram_dqm7 = 0x00000028, |
| 452 | }; |
| 453 | |
| 454 | static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 455 | .grp_ddr_type = 0x000C0000, |
| 456 | .grp_ddrmode_ctl = 0x00020000, |
| 457 | .grp_ddrpke = 0x00000000, |
| 458 | .grp_addds = 0x00000030, |
| 459 | .grp_ctlds = 0x00000030, |
| 460 | .grp_ddrmode = 0x00020000, |
| 461 | .grp_b0ds = 0x00000030, |
| 462 | .grp_b1ds = 0x00000030, |
| 463 | .grp_b2ds = 0x00000030, |
| 464 | .grp_b3ds = 0x00000030, |
| 465 | .grp_b4ds = 0x00000030, |
| 466 | .grp_b5ds = 0x00000030, |
| 467 | .grp_b6ds = 0x00000030, |
| 468 | .grp_b7ds = 0x00000030, |
| 469 | }; |
| 470 | |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 471 | static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
| 472 | .grp_ddr_type = 0x000c0000, |
| 473 | .grp_ddrmode_ctl = 0x00020000, |
| 474 | .grp_ddrpke = 0x00000000, |
| 475 | .grp_addds = 0x00000028, |
| 476 | .grp_ctlds = 0x00000028, |
| 477 | .grp_ddrmode = 0x00020000, |
| 478 | .grp_b0ds = 0x00000028, |
| 479 | .grp_b1ds = 0x00000028, |
| 480 | .grp_b2ds = 0x00000028, |
| 481 | .grp_b3ds = 0x00000028, |
| 482 | .grp_b4ds = 0x00000028, |
| 483 | .grp_b5ds = 0x00000028, |
| 484 | .grp_b6ds = 0x00000028, |
| 485 | .grp_b7ds = 0x00000028, |
| 486 | }; |
| 487 | |
| 488 | /* microSOM with Dual processor and 1GB memory */ |
| 489 | static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = { |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 490 | .p0_mpwldectrl0 = 0x00000000, |
| 491 | .p0_mpwldectrl1 = 0x00000000, |
| 492 | .p1_mpwldectrl0 = 0x00000000, |
| 493 | .p1_mpwldectrl1 = 0x00000000, |
| 494 | .p0_mpdgctrl0 = 0x0314031c, |
| 495 | .p0_mpdgctrl1 = 0x023e0304, |
| 496 | .p1_mpdgctrl0 = 0x03240330, |
| 497 | .p1_mpdgctrl1 = 0x03180260, |
| 498 | .p0_mprddlctl = 0x3630323c, |
| 499 | .p1_mprddlctl = 0x3436283a, |
| 500 | .p0_mpwrdlctl = 0x36344038, |
| 501 | .p1_mpwrdlctl = 0x422a423c, |
| 502 | }; |
| 503 | |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 504 | /* microSOM with Quad processor and 2GB memory */ |
| 505 | static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { |
| 506 | .p0_mpwldectrl0 = 0x00000000, |
| 507 | .p0_mpwldectrl1 = 0x00000000, |
| 508 | .p1_mpwldectrl0 = 0x00000000, |
| 509 | .p1_mpwldectrl1 = 0x00000000, |
| 510 | .p0_mpdgctrl0 = 0x0314031c, |
| 511 | .p0_mpdgctrl1 = 0x023e0304, |
| 512 | .p1_mpdgctrl0 = 0x03240330, |
| 513 | .p1_mpdgctrl1 = 0x03180260, |
| 514 | .p0_mprddlctl = 0x3630323c, |
| 515 | .p1_mprddlctl = 0x3436283a, |
| 516 | .p0_mpwrdlctl = 0x36344038, |
| 517 | .p1_mpwrdlctl = 0x422a423c, |
| 518 | }; |
| 519 | |
| 520 | /* microSOM with Solo processor and 512MB memory */ |
| 521 | static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = { |
| 522 | .p0_mpwldectrl0 = 0x0045004D, |
| 523 | .p0_mpwldectrl1 = 0x003A0047, |
| 524 | .p0_mpdgctrl0 = 0x023C0224, |
| 525 | .p0_mpdgctrl1 = 0x02000220, |
| 526 | .p0_mprddlctl = 0x44444846, |
| 527 | .p0_mpwrdlctl = 0x32343032, |
| 528 | }; |
| 529 | |
| 530 | /* microSOM with Dual lite processor and 1GB memory */ |
| 531 | static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { |
| 532 | .p0_mpwldectrl0 = 0x0045004D, |
| 533 | .p0_mpwldectrl1 = 0x003A0047, |
| 534 | .p1_mpwldectrl0 = 0x001F001F, |
| 535 | .p1_mpwldectrl1 = 0x00210035, |
| 536 | .p0_mpdgctrl0 = 0x023C0224, |
| 537 | .p0_mpdgctrl1 = 0x02000220, |
| 538 | .p1_mpdgctrl0 = 0x02200220, |
Fabio Estevam | dbab8b8 | 2015-05-29 13:00:36 -0300 | [diff] [blame] | 539 | .p1_mpdgctrl1 = 0x02040208, |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 540 | .p0_mprddlctl = 0x44444846, |
| 541 | .p1_mprddlctl = 0x4042463C, |
| 542 | .p0_mpwrdlctl = 0x32343032, |
| 543 | .p1_mpwrdlctl = 0x36363430, |
| 544 | }; |
| 545 | |
| 546 | static struct mx6_ddr3_cfg mem_ddr_2g = { |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 547 | .mem_speed = 1600, |
| 548 | .density = 2, |
| 549 | .width = 16, |
| 550 | .banks = 8, |
| 551 | .rowaddr = 14, |
| 552 | .coladdr = 10, |
| 553 | .pagesz = 2, |
| 554 | .trcd = 1375, |
| 555 | .trcmin = 4875, |
| 556 | .trasmin = 3500, |
| 557 | .SRT = 1, |
| 558 | }; |
| 559 | |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 560 | static struct mx6_ddr3_cfg mem_ddr_4g = { |
| 561 | .mem_speed = 1600, |
| 562 | .density = 4, |
| 563 | .width = 16, |
| 564 | .banks = 8, |
| 565 | .rowaddr = 15, |
| 566 | .coladdr = 10, |
| 567 | .pagesz = 2, |
| 568 | .trcd = 1375, |
| 569 | .trcmin = 4875, |
| 570 | .trasmin = 3500, |
| 571 | }; |
| 572 | |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 573 | static void ccgr_init(void) |
| 574 | { |
| 575 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 576 | |
| 577 | writel(0x00C03F3F, &ccm->CCGR0); |
| 578 | writel(0x0030FC03, &ccm->CCGR1); |
| 579 | writel(0x0FFFC000, &ccm->CCGR2); |
| 580 | writel(0x3FF00000, &ccm->CCGR3); |
| 581 | writel(0x00FFF300, &ccm->CCGR4); |
| 582 | writel(0x0F0000C3, &ccm->CCGR5); |
| 583 | writel(0x000003FF, &ccm->CCGR6); |
| 584 | } |
| 585 | |
| 586 | static void gpr_init(void) |
| 587 | { |
| 588 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 589 | |
| 590 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 591 | writel(0xF00000CF, &iomux->gpr[4]); |
| 592 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 593 | writel(0x007F007F, &iomux->gpr[6]); |
| 594 | writel(0x007F007F, &iomux->gpr[7]); |
| 595 | } |
| 596 | |
| 597 | /* |
| 598 | * This section requires the differentiation between Solidrun mx6 boards, but |
| 599 | * for now, it will configure only for the mx6dual hummingboard version. |
| 600 | */ |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 601 | static void spl_dram_init(int width) |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 602 | { |
| 603 | struct mx6_ddr_sysinfo sysinfo = { |
| 604 | /* width of data bus: 0=16, 1=32, 2=64 */ |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 605 | .dsize = width / 32, |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 606 | /* config for full 4GB range so that get_mem_size() works */ |
| 607 | .cs_density = 32, /* 32Gb per CS */ |
| 608 | .ncs = 1, /* single chip select */ |
| 609 | .cs1_mirror = 0, |
| 610 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
| 611 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
| 612 | .walat = 1, /* Write additional latency */ |
| 613 | .ralat = 5, /* Read additional latency */ |
| 614 | .mif3_mode = 3, /* Command prediction working mode */ |
| 615 | .bi_on = 1, /* Bank interleaving enabled */ |
| 616 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| 617 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| 618 | }; |
| 619 | |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 620 | if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) |
| 621 | mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); |
| 622 | else |
| 623 | mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); |
| 624 | |
| 625 | if (is_cpu_type(MXC_CPU_MX6D)) |
| 626 | mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); |
| 627 | else if (is_cpu_type(MXC_CPU_MX6Q)) |
| 628 | mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); |
| 629 | else if (is_cpu_type(MXC_CPU_MX6DL)) |
Fabio Estevam | dbab8b8 | 2015-05-29 13:00:36 -0300 | [diff] [blame] | 630 | mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 631 | else if (is_cpu_type(MXC_CPU_MX6SOLO)) |
| 632 | mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | void board_init_f(ulong dummy) |
| 636 | { |
| 637 | /* setup AIPS and disable watchdog */ |
| 638 | arch_cpu_init(); |
| 639 | |
| 640 | ccgr_init(); |
| 641 | gpr_init(); |
| 642 | |
| 643 | /* iomux and setup of i2c */ |
| 644 | board_early_init_f(); |
| 645 | |
| 646 | /* setup GP timer */ |
| 647 | timer_init(); |
| 648 | |
| 649 | /* UART clocks enabled and gd valid - init serial console */ |
| 650 | preloader_console_init(); |
| 651 | |
| 652 | /* DDR initialization */ |
Fabio Estevam | 8cb6817 | 2015-04-25 18:47:18 -0300 | [diff] [blame] | 653 | if (is_cpu_type(MXC_CPU_MX6SOLO)) |
| 654 | spl_dram_init(32); |
| 655 | else |
| 656 | spl_dram_init(64); |
Fabio Estevam | b8ce6fe | 2015-04-20 14:48:57 -0300 | [diff] [blame] | 657 | |
| 658 | /* Clear the BSS. */ |
| 659 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 660 | |
| 661 | /* load/boot image from boot device */ |
| 662 | board_init_r(NULL, 0); |
| 663 | } |
| 664 | #endif |