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Stefan Roese5e7abce2010-09-11 09:31:43 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef _PPC440SPE_H_
22#define _PPC440SPE_H_
23
24#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
25
Stefan Roese5e7abce2010-09-11 09:31:43 +020026/*
27 * Some SoC specific registers (not common for all 440 SoC's)
28 */
29
Stefan Roese550650d2010-09-20 16:05:31 +020030/* Memory mapped register */
31#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
Stefan Roese5e7abce2010-09-11 09:31:43 +020032
Stefan Roese550650d2010-09-20 16:05:31 +020033#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
35
36#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
37
38/* SDR's */
Stefan Roese5e7abce2010-09-11 09:31:43 +020039#define SDR0_PCI0 0x0300
40#define SDR0_SDSTP2 0x0022
41#define SDR0_SDSTP3 0x0023
42
43#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
44#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
45#define SDR0_SDSTP1_ERPN_MASK (0x80000000 >> 12)
46#define SDR0_SDSTP1_ERPN_EBC 0
47#define SDR0_SDSTP1_ERPN_PCI (0x80000000 >> 12)
48#define SDR0_SDSTP1_EBCW_MASK (0x80000000 >> 24)
49#define SDR0_SDSTP1_EBCW_8_BITS 0
50#define SDR0_SDSTP1_EBCW_16_BITS (0x80000000 >> 24)
51
52#define SDR0_PFC1_EM_1000 (0x80000000 >> 10)
53
54#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */
55
56#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
57#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0
58 (EBC boot) */
59#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1
60 (PCI boot) */
61#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled -
62 Addr = 0x54 */
63#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled -
64 Addr = 0x50 */
65
66#define SDR0_SRST0_DMC 0x00200000
67
68#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
69#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
70#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
71#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
72#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
73#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
74#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
75#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
76#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
77
78#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
79#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
80#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
81#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
82#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
83#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
84
85#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
Mike Williams16263082011-07-22 04:01:30 +000086#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
Stefan Roese5e7abce2010-09-11 09:31:43 +020087#define PRADV_MASK 0x07000000 /* Primary Divisor A */
88#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
89#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
90
91/* Strap 1 Register */
92#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
93#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
94#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
95#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
Mike Williams16263082011-07-22 04:01:30 +000096#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
Stefan Roese5e7abce2010-09-11 09:31:43 +020097#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
98#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
99#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
100#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
101#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
102#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
103#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
104#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
105#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
106#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
107#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
108#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
109#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
110
111#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
112#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
113
114#endif /* _PPC440SPE_H_ */