| Simon Glass | 5cfc662 | 2015-01-05 20:05:25 -0700 | [diff] [blame] | 1 | NVIDIA Tegra GPIO controller |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : "nvidia,tegra<chip>-gpio" |
| 5 | - reg : Physical base address and length of the controller's registers. |
| 6 | - interrupts : The interrupt outputs from the controller. For Tegra20, |
| 7 | there should be 7 interrupts specified, and for Tegra30, there should |
| 8 | be 8 interrupts specified. |
| 9 | - #gpio-cells : Should be two. The first cell is the pin number and the |
| 10 | second cell is used to specify optional parameters: |
| 11 | - bit 0 specifies polarity (0 for normal, 1 for inverted) |
| 12 | - gpio-controller : Marks the device node as a GPIO controller. |
| 13 | - #interrupt-cells : Should be 2. |
| 14 | The first cell is the GPIO number. |
| 15 | The second cell is used to specify flags: |
| 16 | bits[3:0] trigger type and level flags: |
| 17 | 1 = low-to-high edge triggered. |
| 18 | 2 = high-to-low edge triggered. |
| 19 | 4 = active high level-sensitive. |
| 20 | 8 = active low level-sensitive. |
| 21 | Valid combinations are 1, 2, 3, 4, 8. |
| 22 | - interrupt-controller : Marks the device node as an interrupt controller. |
| 23 | |
| 24 | Example: |
| 25 | |
| 26 | gpio: gpio@6000d000 { |
| 27 | compatible = "nvidia,tegra20-gpio"; |
| 28 | reg = < 0x6000d000 0x1000 >; |
| 29 | interrupts = < 0 32 0x04 |
| 30 | 0 33 0x04 |
| 31 | 0 34 0x04 |
| 32 | 0 35 0x04 |
| 33 | 0 55 0x04 |
| 34 | 0 87 0x04 |
| 35 | 0 89 0x04 >; |
| 36 | #gpio-cells = <2>; |
| 37 | gpio-controller; |
| 38 | #interrupt-cells = <2>; |
| 39 | interrupt-controller; |
| 40 | }; |