| wdenk | 0e6d798 | 2004-03-14 00:07:33 +0000 | [diff] [blame] | 1 | /* |
| Stefan Roese | 56fb6ba | 2006-10-04 07:12:49 +0200 | [diff] [blame] | 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * |
| Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 56fb6ba | 2006-10-04 07:12:49 +0200 | [diff] [blame] | 5 | */ |
| wdenk | 0e6d798 | 2004-03-14 00:07:33 +0000 | [diff] [blame] | 6 | |
| 7 | #include <ppc_asm.tmpl> |
| 8 | #include <config.h> |
| Peter Tyser | 61f2b38 | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 9 | #include <asm/mmu.h> |
| Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 10 | #include <asm/ppc4xx.h> |
| wdenk | 0e6d798 | 2004-03-14 00:07:33 +0000 | [diff] [blame] | 11 | |
| 12 | /************************************************************************** |
| 13 | * TLB TABLE |
| 14 | * |
| 15 | * This table is used by the cpu boot code to setup the initial tlb |
| 16 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 17 | * this table lets each board set things up however they like. |
| 18 | * |
| 19 | * Pointer to the table is returned in r1 |
| 20 | * |
| 21 | *************************************************************************/ |
| 22 | |
| Stefan Roese | fa1aef1 | 2007-03-07 16:43:00 +0100 | [diff] [blame] | 23 | .section .bootpg,"ax" |
| 24 | .globl tlbtab |
| wdenk | 0e6d798 | 2004-03-14 00:07:33 +0000 | [diff] [blame] | 25 | |
| 26 | tlbtab: |
| Stefan Roese | fa1aef1 | 2007-03-07 16:43:00 +0100 | [diff] [blame] | 27 | tlbtab_start |
| 28 | |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 29 | tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
| Stefan Roese | fa1aef1 | 2007-03-07 16:43:00 +0100 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * TLB entries for SDRAM are not needed on this platform. |
| 33 | * They are dynamically generated in the SPD DDR(2) detection |
| 34 | * routine. |
| 35 | */ |
| 36 | |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 37 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
| 38 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) |
| 39 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) |
| 40 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) |
| 41 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) |
| Stefan Roese | fa1aef1 | 2007-03-07 16:43:00 +0100 | [diff] [blame] | 42 | tlbtab_end |