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Stefan Roese8a316c92005-08-01 16:49:12 +02001/*
Stefan Roese8b395012007-04-29 14:13:01 +02002 * (C) Copyright 2005-2007
Stefan Roese8a316c92005-08-01 16:49:12 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * bamboo.h - configuration for BAMBOO board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +020033#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
Stefan Roese846b0dd2005-08-08 12:42:22 +020034#define CONFIG_440EP 1 /* Specific PPC440EP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020035#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese17f50f222005-08-04 17:09:16 +020036#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese8a316c92005-08-01 16:49:12 +020037#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
38
Stefan Roese490f2042008-06-06 15:55:03 +020039/*
40 * Include common defines/options for all AMCC eval boards
41 */
42#define CONFIG_HOSTNAME bamboo
43#include "amcc-common.h"
44
Stefan Roesec57c7982005-08-11 17:56:56 +020045#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
46
47/*
48 * Please note that, if NAND support is enabled, the 2nd ethernet port
49 * can't be used because of pin multiplexing. So, if you want to use the
50 * 2nd ethernet port you have to "undef" the following define.
51 */
52#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
53
Stefan Roese8a316c92005-08-01 16:49:12 +020054/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
59#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
60#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
61#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
62#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese8a316c92005-08-01 16:49:12 +020063
64/*Don't change either of these*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
66#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roese8a316c92005-08-01 16:49:12 +020067/*Don't change either of these*/
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_USB_DEVICE 0x50000000
70#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
71#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
72#define CONFIG_SYS_NAND_ADDR 0x90000000
73#define CONFIG_SYS_NAND2_ADDR 0x94000000
Stefan Roese8a316c92005-08-01 16:49:12 +020074
75/*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer (placed in SDRAM)
77 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
79#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
80#define CONFIG_SYS_INIT_RAM_END (4 << 10)
81#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
82#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
83#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese8a316c92005-08-01 16:49:12 +020084
Stefan Roese8a316c92005-08-01 16:49:12 +020085/*-----------------------------------------------------------------------
86 * Serial Port
87 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
Stefan Roese17f50f222005-08-04 17:09:16 +020089/* define this if you want console on UART1 */
Stefan Roese8a316c92005-08-01 16:49:12 +020090#undef CONFIG_UART1_CONSOLE
91
Stefan Roese8a316c92005-08-01 16:49:12 +020092/*-----------------------------------------------------------------------
93 * NVRAM/RTC
94 *
95 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
96 * The DS1558 code assumes this condition
97 *
98 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
Stefan Roese17f50f222005-08-04 17:09:16 +0200100#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
101
102/*-----------------------------------------------------------------------
103 * Environment
104 *----------------------------------------------------------------------*/
Stefan Roesecf959c72007-06-01 15:27:11 +0200105#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200106#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese17f50f222005-08-04 17:09:16 +0200107#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200108#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200109#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese17f50f222005-08-04 17:09:16 +0200110#endif
Stefan Roese8a316c92005-08-01 16:49:12 +0200111
112/*-----------------------------------------------------------------------
113 * FLASH related
114 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
116#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Stefan Roese8a316c92005-08-01 16:49:12 +0200117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#undef CONFIG_SYS_FLASH_CHECKSUM
119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese8a316c92005-08-01 16:49:12 +0200121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_ADDR0 0x555
123#define CONFIG_SYS_FLASH_ADDR1 0x2aa
124#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese17f50f222005-08-04 17:09:16 +0200125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
127#define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
Stefan Roese17f50f222005-08-04 17:09:16 +0200128
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200129#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200130#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200132#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese17f50f222005-08-04 17:09:16 +0200133
Stefan Roese17f50f222005-08-04 17:09:16 +0200134/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200135#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200137#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200138
Stefan Roesecf959c72007-06-01 15:27:11 +0200139/*
140 * IPL (Initial Program Loader, integrated inside CPU)
141 * Will load first 4k from NAND (SPL) into cache and execute it from there.
142 *
143 * SPL (Secondary Program Loader)
144 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
145 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
146 * controller and the NAND controller so that the special U-Boot image can be
147 * loaded from NAND to SDRAM.
148 *
149 * NUB (NAND U-Boot)
150 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
151 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
152 *
153 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
154 * set up. While still running from cache, I experienced problems accessing
155 * the NAND controller. sr - 2006-08-25
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
158#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
159#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
160#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
161#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
162#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roesecf959c72007-06-01 15:27:11 +0200163
164/*
165 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
168#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Stefan Roesecf959c72007-06-01 15:27:11 +0200169
170/*
171 * Now the NAND chip has to be defined (no autodetection used!)
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
174#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
175#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
176#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
177#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
Stefan Roesecf959c72007-06-01 15:27:11 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_NAND_ECCSIZE 256
180#define CONFIG_SYS_NAND_ECCBYTES 3
181#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
182#define CONFIG_SYS_NAND_OOBSIZE 16
183#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
184#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Stefan Roesecf959c72007-06-01 15:27:11 +0200185
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200186#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roesecf959c72007-06-01 15:27:11 +0200187/*
188 * For NAND booting the environment is embedded in the U-Boot image. Please take
189 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
192#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200193#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roesecf959c72007-06-01 15:27:11 +0200194#endif
195
Stefan Roese8a316c92005-08-01 16:49:12 +0200196/*-----------------------------------------------------------------------
Stefan Roese8b395012007-04-29 14:13:01 +0200197 * NAND FLASH
Stefan Roesec57c7982005-08-11 17:56:56 +0200198 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MAX_NAND_DEVICE 2
200#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
201#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
202#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
203#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roesec57c7982005-08-11 17:56:56 +0200204
Stefan Roesecf959c72007-06-01 15:27:11 +0200205#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NAND_CS 1
Stefan Roesecf959c72007-06-01 15:27:11 +0200207#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Stefan Roesecf959c72007-06-01 15:27:11 +0200209/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_EBC_PB0AP 0x018003c0
211#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roesecf959c72007-06-01 15:27:11 +0200212#endif
213
Stefan Roesec57c7982005-08-11 17:56:56 +0200214/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200215 * DDR SDRAM
Stefan Roese17f50f222005-08-04 17:09:16 +0200216 *----------------------------------------------------------------------------- */
217#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Stefan Roesefd49bf02005-11-15 16:04:58 +0100218#undef CONFIG_DDR_ECC /* don't use ECC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
220#define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
221#define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
Eugene OBriend2f68002007-07-31 10:24:56 +0200222#define CONFIG_PROG_SDRAM_TLB
Stefan Roese8a316c92005-08-01 16:49:12 +0200223
224/*-----------------------------------------------------------------------
225 * I2C
226 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese8a316c92005-08-01 16:49:12 +0200228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_I2C_MULTI_EEPROMS
230#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
231#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
232#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
233#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese8a316c92005-08-01 16:49:12 +0200234
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200235#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200236#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
237#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200238#endif /* CONFIG_ENV_IS_IN_EEPROM */
Stefan Roese17f50f222005-08-04 17:09:16 +0200239
Stefan Roese490f2042008-06-06 15:55:03 +0200240/*
241 * Default environment variables
242 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200243#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200244 CONFIG_AMCC_DEF_ENV \
245 CONFIG_AMCC_DEF_ENV_POWERPC \
246 CONFIG_AMCC_DEF_ENV_PPC_OLD \
247 CONFIG_AMCC_DEF_ENV_NOR_UPD \
248 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese17f50f222005-08-04 17:09:16 +0200249 "kernel_addr=fff00000\0" \
250 "ramdisk_addr=fff10000\0" \
Stefan Roese17f50f222005-08-04 17:09:16 +0200251 ""
Stefan Roese8a316c92005-08-01 16:49:12 +0200252
Stefan Roesea00eccf2008-05-08 11:05:15 +0200253#define CONFIG_HAS_ETH0
Stefan Roese17f50f222005-08-04 17:09:16 +0200254#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200255#define CONFIG_PHY1_ADDR 1
Stefan Roesec57c7982005-08-11 17:56:56 +0200256
257#ifndef CONFIG_BAMBOO_NAND
Stefan Roese8a316c92005-08-01 16:49:12 +0200258#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Stefan Roesec57c7982005-08-11 17:56:56 +0200259#endif /* CONFIG_BAMBOO_NAND */
260
Stefan Roese846b0dd2005-08-08 12:42:22 +0200261#ifdef CONFIG_440EP
Stefan Roese8a316c92005-08-01 16:49:12 +0200262/* USB */
263#define CONFIG_USB_OHCI
264#define CONFIG_USB_STORAGE
265
266/*Comment this out to enable USB 1.1 device*/
267#define USB_2_0_DEVICE
Stefan Roese846b0dd2005-08-08 12:42:22 +0200268#endif /*CONFIG_440EP*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200269
Jon Loeligerba2351f2007-07-04 22:31:49 -0500270/*
Stefan Roese490f2042008-06-06 15:55:03 +0200271 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500272 */
Jon Loeligerba2351f2007-07-04 22:31:49 -0500273#define CONFIG_CMD_DATE
Jon Loeligerba2351f2007-07-04 22:31:49 -0500274#define CONFIG_CMD_EXT2
Stefan Roese490f2042008-06-06 15:55:03 +0200275#define CONFIG_CMD_FAT
276#define CONFIG_CMD_PCI
277#define CONFIG_CMD_SDRAM
Jon Loeligerba2351f2007-07-04 22:31:49 -0500278#define CONFIG_CMD_SNTP
Stefan Roese490f2042008-06-06 15:55:03 +0200279#define CONFIG_CMD_USB
Jon Loeligerba2351f2007-07-04 22:31:49 -0500280
281#ifdef CONFIG_BAMBOO_NAND
282#define CONFIG_CMD_NAND
283#endif
284
Stefan Roese3b6748e2005-10-14 15:37:34 +0200285#define CONFIG_SUPPORT_VFAT
286
Stefan Roese490f2042008-06-06 15:55:03 +0200287/* Partitions */
288#define CONFIG_MAC_PARTITION
289#define CONFIG_DOS_PARTITION
290#define CONFIG_ISO_PARTITION
Stefan Roese193dd952006-07-27 16:14:05 +0200291
Stefan Roese8a316c92005-08-01 16:49:12 +0200292/*-----------------------------------------------------------------------
293 * PCI stuff
294 *-----------------------------------------------------------------------
295 */
296/* General PCI */
Stefan Roesec57c7982005-08-11 17:56:56 +0200297#define CONFIG_PCI /* include pci support */
298#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Stefan Roese17f50f222005-08-04 17:09:16 +0200299#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200301
302/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCI_TARGET_INIT
304#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese8a316c92005-08-01 16:49:12 +0200305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
307#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese8a316c92005-08-01 16:49:12 +0200308
Stefan Roese8a316c92005-08-01 16:49:12 +0200309#endif /* __CONFIG_H */