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TsiChungLiew4a442d32007-08-16 19:23:50 -05001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30
31#include <asm/immap.h>
32
33/*
34 * Breath some life into the CPU...
35 *
36 * Set up the memory map,
37 * initialize a bunch of registers,
38 * initialize the UPM's
39 */
40void cpu_init_f(void)
41{
42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
44 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
45 volatile scm_t *scm = (scm_t *) MMAP_SCM;
46
47 /* watchdog is enabled by default - disable the watchdog */
48#ifndef CONFIG_WATCHDOG
49 wdog->cr = 0;
50#endif
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
TsiChungLiew4a442d32007-08-16 19:23:50 -050053
54 /* Port configuration */
55 gpio->par_cs = 0;
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
58 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
59 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
60 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050061#endif
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050064 gpio->par_cs |= GPIO_PAR_CS_CS1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
66 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
67 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050068#endif
69
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050071 gpio->par_cs |= GPIO_PAR_CS_CS2;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
73 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
74 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050075#endif
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050078 gpio->par_cs |= GPIO_PAR_CS_CS3;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
80 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
81 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050082#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050085 gpio->par_cs |= GPIO_PAR_CS_CS4;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
87 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
88 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050089#endif
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050092 gpio->par_cs |= GPIO_PAR_CS_CS5;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
94 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
95 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -050096#endif
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -050099 gpio->par_cs |= GPIO_PAR_CS_CS6;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 fbcs->csar6 = CONFIG_SYS_CS6_BASE;
101 fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
102 fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -0500103#endif
104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
TsiChungLiew4a442d32007-08-16 19:23:50 -0500106 gpio->par_cs |= GPIO_PAR_CS_CS7;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 fbcs->csar7 = CONFIG_SYS_CS7_BASE;
108 fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
109 fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
TsiChungLiew4a442d32007-08-16 19:23:50 -0500110#endif
111
112#ifdef CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
114 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
TsiChungLiew4a442d32007-08-16 19:23:50 -0500115#endif
116
117 icache_enable();
118}
119
120/*
121 * initialize higher level parts of CPU like timers
122 */
123int cpu_init_r(void)
124{
125 return (0);
126}
127
128void uart_port_conf(void)
129{
Stefan Roese8280f6a2007-08-18 14:33:02 +0200130 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
TsiChungLiew4a442d32007-08-16 19:23:50 -0500131
Stefan Roese8280f6a2007-08-18 14:33:02 +0200132 /* Setup Ports: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 switch (CONFIG_SYS_UART_PORT) {
Stefan Roese8280f6a2007-08-18 14:33:02 +0200134 case 0:
135 gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
136 break;
137 case 1:
138 gpio->par_uart =
139 (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
140 break;
141 case 2:
142 gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
143 break;
144 }
TsiChungLiew4a442d32007-08-16 19:23:50 -0500145}