| Jimmy Zhang | 0e35ad0 | 2012-04-02 13:18:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| 3 | * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Jimmy Zhang | 0e35ad0 | 2012-04-02 13:18:52 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _ARCH_EMC_H_ |
| 9 | #define _ARCH_EMC_H_ |
| 10 | |
| 11 | #include <asm/types.h> |
| 12 | |
| 13 | #define TEGRA_EMC_NUM_REGS 46 |
| 14 | |
| 15 | /* EMC Registers */ |
| 16 | struct emc_ctlr { |
| 17 | u32 cfg; /* 0x00: EMC_CFG */ |
| 18 | u32 reserved0[3]; /* 0x04 ~ 0x0C */ |
| 19 | u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ |
| 20 | u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ |
| 21 | u32 reserved1[2]; /* 0x18 ~ 0x18 */ |
| 22 | u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ |
| 23 | u32 pin; /* 0x24: EMC_PIN */ |
| 24 | u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ |
| 25 | u32 rc; /* 0x2C: EMC_RC */ |
| 26 | u32 rfc; /* 0x30: EMC_RFC */ |
| 27 | u32 ras; /* 0x34: EMC_RAS */ |
| 28 | u32 rp; /* 0x38: EMC_RP */ |
| 29 | u32 r2w; /* 0x3C: EMC_R2W */ |
| 30 | u32 w2r; /* 0x40: EMC_W2R */ |
| 31 | u32 r2p; /* 0x44: EMC_R2P */ |
| 32 | u32 w2p; /* 0x48: EMC_W2P */ |
| 33 | u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ |
| 34 | u32 wd_rcd; /* 0x50: EMC_WD_RCD */ |
| 35 | u32 rrd; /* 0x54: EMC_RRD */ |
| 36 | u32 rext; /* 0x58: EMC_REXT */ |
| 37 | u32 wdv; /* 0x5C: EMC_WDV */ |
| 38 | u32 quse; /* 0x60: EMC_QUSE */ |
| 39 | u32 qrst; /* 0x64: EMC_QRST */ |
| 40 | u32 qsafe; /* 0x68: EMC_QSAFE */ |
| 41 | u32 rdv; /* 0x6C: EMC_RDV */ |
| 42 | u32 refresh; /* 0x70: EMC_REFRESH */ |
| 43 | u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ |
| 44 | u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ |
| 45 | u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ |
| 46 | u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ |
| 47 | u32 act2pden; /* 0x84: EMC_ACT2PDEN */ |
| 48 | u32 ar2pden; /* 0x88: EMC_AR2PDEN */ |
| 49 | u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ |
| 50 | u32 txsr; /* 0x90: EMC_TXSR */ |
| 51 | u32 tcke; /* 0x94: EMC_TCKE */ |
| 52 | u32 tfaw; /* 0x98: EMC_TFAW */ |
| 53 | u32 trpab; /* 0x9C: EMC_TRPAB */ |
| 54 | u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ |
| 55 | u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ |
| 56 | u32 trefbw; /* 0xA8: EMC_TREFBW */ |
| 57 | u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ |
| 58 | u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ |
| 59 | u32 odt_read; /* 0xB4: EMC_ODT_READ */ |
| 60 | u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ |
| 61 | u32 mrs; /* 0xCC: EMC_MRS */ |
| 62 | u32 emrs; /* 0xD0: EMC_EMRS */ |
| 63 | u32 ref; /* 0xD4: EMC_REF */ |
| 64 | u32 pre; /* 0xD8: EMC_PRE */ |
| 65 | u32 nop; /* 0xDC: EMC_NOP */ |
| 66 | u32 self_ref; /* 0xE0: EMC_SELF_REF */ |
| 67 | u32 dpd; /* 0xE4: EMC_DPD */ |
| 68 | u32 mrw; /* 0xE8: EMC_MRW */ |
| 69 | u32 mrr; /* 0xEC: EMC_MRR */ |
| 70 | u32 reserved3; /* 0xF0: */ |
| 71 | u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ |
| 72 | u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ |
| 73 | u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ |
| 74 | u32 fbio_spare; /* 0x100: SBIO_SPARE */ |
| 75 | /* There are more registers ... */ |
| 76 | }; |
| 77 | |
| 78 | /** |
| 79 | * Set up the EMC for the given rate. The timing parameters are retrieved |
| 80 | * from the device tree "nvidia,tegra20-emc" node and its |
| 81 | * "nvidia,tegra20-emc-table" sub-nodes. |
| 82 | * |
| 83 | * @param blob Device tree blob |
| 84 | * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) |
| 85 | * @return 0 if ok, else -ve error code (look in emc.c to decode it) |
| 86 | */ |
| 87 | int tegra_set_emc(const void *blob, unsigned rate); |
| 88 | |
| 89 | /** |
| 90 | * Get a pointer to the EMC controller from the device tree. |
| 91 | * |
| 92 | * @param blob Device tree blob |
| 93 | * @return pointer to EMC controller |
| 94 | */ |
| 95 | struct emc_ctlr *emc_get_controller(const void *blob); |
| 96 | |
| 97 | #endif |