Hans de Goede | d6e6d4b | 2015-11-20 16:03:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> |
| 3 | * |
| 4 | * This file is dual-licensed: you can use it either under the terms |
| 5 | * of the GPL or the X11 license, at your option. Note that this dual |
| 6 | * licensing only applies to this file, and not this project as a |
| 7 | * whole. |
| 8 | * |
| 9 | * a) This file is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of the |
| 12 | * License, or (at your option) any later version. |
| 13 | * |
| 14 | * This file is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * Or, alternatively, |
| 20 | * |
| 21 | * b) Permission is hereby granted, free of charge, to any person |
| 22 | * obtaining a copy of this software and associated documentation |
| 23 | * files (the "Software"), to deal in the Software without |
| 24 | * restriction, including without limitation the rights to use, |
| 25 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 26 | * sell copies of the Software, and to permit persons to whom the |
| 27 | * Software is furnished to do so, subject to the following |
| 28 | * conditions: |
| 29 | * |
| 30 | * The above copyright notice and this permission notice shall be |
| 31 | * included in all copies or substantial portions of the Software. |
| 32 | * |
| 33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 40 | * OTHER DEALINGS IN THE SOFTWARE. |
| 41 | */ |
| 42 | |
| 43 | #include "skeleton.dtsi" |
| 44 | |
| 45 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 46 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
| 47 | |
| 48 | / { |
| 49 | interrupt-parent = <&gic>; |
| 50 | |
| 51 | cpus { |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | |
| 55 | cpu@0 { |
| 56 | compatible = "arm,cortex-a7"; |
| 57 | device_type = "cpu"; |
| 58 | reg = <0>; |
| 59 | }; |
| 60 | |
| 61 | cpu@1 { |
| 62 | compatible = "arm,cortex-a7"; |
| 63 | device_type = "cpu"; |
| 64 | reg = <1>; |
| 65 | }; |
| 66 | |
| 67 | cpu@2 { |
| 68 | compatible = "arm,cortex-a7"; |
| 69 | device_type = "cpu"; |
| 70 | reg = <2>; |
| 71 | }; |
| 72 | |
| 73 | cpu@3 { |
| 74 | compatible = "arm,cortex-a7"; |
| 75 | device_type = "cpu"; |
| 76 | reg = <3>; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | timer { |
| 81 | compatible = "arm,armv7-timer"; |
| 82 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 83 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 84 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 85 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 86 | clock-frequency = <24000000>; |
| 87 | arm,cpu-registers-not-fw-configured; |
| 88 | }; |
| 89 | |
| 90 | memory { |
| 91 | reg = <0x40000000 0x80000000>; |
| 92 | }; |
| 93 | |
| 94 | clocks { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <1>; |
| 97 | ranges; |
| 98 | |
| 99 | osc24M: osc24M_clk { |
| 100 | #clock-cells = <0>; |
| 101 | compatible = "fixed-clock"; |
| 102 | clock-frequency = <24000000>; |
| 103 | clock-output-names = "osc24M"; |
| 104 | }; |
| 105 | |
| 106 | osc32k: osc32k_clk { |
| 107 | #clock-cells = <0>; |
| 108 | compatible = "fixed-clock"; |
| 109 | clock-frequency = <32768>; |
| 110 | clock-output-names = "osc32k"; |
| 111 | }; |
| 112 | |
| 113 | pll1: clk@01c20000 { |
| 114 | #clock-cells = <0>; |
| 115 | compatible = "allwinner,sun8i-a23-pll1-clk"; |
| 116 | reg = <0x01c20000 0x4>; |
| 117 | clocks = <&osc24M>; |
| 118 | clock-output-names = "pll1"; |
| 119 | }; |
| 120 | |
| 121 | /* dummy clock until actually implemented */ |
| 122 | pll5: pll5_clk { |
| 123 | #clock-cells = <0>; |
| 124 | compatible = "fixed-clock"; |
| 125 | clock-frequency = <0>; |
| 126 | clock-output-names = "pll5"; |
| 127 | }; |
| 128 | |
| 129 | pll6: clk@01c20028 { |
| 130 | #clock-cells = <1>; |
| 131 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
| 132 | reg = <0x01c20028 0x4>; |
| 133 | clocks = <&osc24M>; |
| 134 | clock-output-names = "pll6", "pll6x2", "pll6d2"; |
| 135 | }; |
| 136 | |
| 137 | pll8: clk@01c20044 { |
| 138 | #clock-cells = <1>; |
| 139 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
| 140 | reg = <0x01c20044 0x4>; |
| 141 | clocks = <&osc24M>; |
| 142 | clock-output-names = "pll8", "pll8x2"; |
| 143 | }; |
| 144 | |
| 145 | cpu: cpu_clk@01c20050 { |
| 146 | #clock-cells = <0>; |
| 147 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 148 | reg = <0x01c20050 0x4>; |
| 149 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; |
| 150 | clock-output-names = "cpu"; |
| 151 | }; |
| 152 | |
| 153 | axi: axi_clk@01c20050 { |
| 154 | #clock-cells = <0>; |
| 155 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 156 | reg = <0x01c20050 0x4>; |
| 157 | clocks = <&cpu>; |
| 158 | clock-output-names = "axi"; |
| 159 | }; |
| 160 | |
| 161 | ahb1: ahb1_clk@01c20054 { |
| 162 | #clock-cells = <0>; |
| 163 | compatible = "allwinner,sun6i-a31-ahb1-clk"; |
| 164 | reg = <0x01c20054 0x4>; |
| 165 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; |
| 166 | clock-output-names = "ahb1"; |
| 167 | }; |
| 168 | |
| 169 | ahb2: ahb2_clk@01c2005c { |
| 170 | #clock-cells = <0>; |
| 171 | compatible = "allwinner,sun8i-h3-ahb2-clk"; |
| 172 | reg = <0x01c2005c 0x4>; |
| 173 | clocks = <&ahb1>, <&pll6 2>; |
| 174 | clock-output-names = "ahb2"; |
| 175 | }; |
| 176 | |
| 177 | apb1: apb1_clk@01c20054 { |
| 178 | #clock-cells = <0>; |
| 179 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 180 | reg = <0x01c20054 0x4>; |
| 181 | clocks = <&ahb1>; |
| 182 | clock-output-names = "apb1"; |
| 183 | }; |
| 184 | |
| 185 | apb2: apb2_clk@01c20058 { |
| 186 | #clock-cells = <0>; |
| 187 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 188 | reg = <0x01c20058 0x4>; |
| 189 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
| 190 | clock-output-names = "apb2"; |
| 191 | }; |
| 192 | |
| 193 | bus_gates: clk@01c20060 { |
| 194 | #clock-cells = <1>; |
| 195 | compatible = "allwinner,sun8i-h3-bus-gates-clk"; |
| 196 | reg = <0x01c20060 0x14>; |
| 197 | clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; |
| 198 | clock-names = "ahb1", "ahb2", "apb1", "apb2"; |
| 199 | clock-indices = <5>, <6>, <8>, |
| 200 | <9>, <10>, <13>, |
| 201 | <14>, <17>, <18>, |
| 202 | <19>, <20>, |
| 203 | <21>, <23>, |
| 204 | <24>, <25>, |
| 205 | <26>, <27>, |
| 206 | <28>, <29>, |
| 207 | <30>, <31>, <32>, |
| 208 | <35>, <36>, <37>, |
| 209 | <40>, <41>, <43>, |
| 210 | <44>, <52>, <53>, |
| 211 | <54>, <64>, |
| 212 | <65>, <69>, <72>, |
| 213 | <76>, <77>, <78>, |
| 214 | <96>, <97>, <98>, |
| 215 | <112>, <113>, |
| 216 | <114>, <115>, <116>, |
| 217 | <128>, <135>; |
| 218 | clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", |
| 219 | "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", |
| 220 | "ahb1_sdram", "ahb2_gmac", "ahb1_ts", |
| 221 | "ahb1_hstimer", "ahb1_spi0", |
| 222 | "ahb1_spi1", "ahb1_otg", |
| 223 | "ahb1_otg_ehci0", "ahb1_ehic1", |
| 224 | "ahb1_ehic2", "ahb1_ehic3", |
| 225 | "ahb1_otg_ohci0", "ahb2_ohic1", |
| 226 | "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", |
| 227 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", |
| 228 | "ahb1_csi", "ahb1_tve", "ahb1_hdmi", |
| 229 | "ahb1_de", "ahb1_gpu", "ahb1_msgbox", |
| 230 | "ahb1_spinlock", "apb1_codec", |
| 231 | "apb1_spdif", "apb1_pio", "apb1_ths", |
| 232 | "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", |
| 233 | "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", |
| 234 | "apb2_uart0", "apb2_uart1", |
| 235 | "apb2_uart2", "apb2_uart3", "apb2_scr", |
| 236 | "ahb1_ephy", "ahb1_dbg"; |
| 237 | }; |
| 238 | |
| 239 | mmc0_clk: clk@01c20088 { |
| 240 | #clock-cells = <1>; |
| 241 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
| 242 | reg = <0x01c20088 0x4>; |
| 243 | clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
| 244 | clock-output-names = "mmc0", |
| 245 | "mmc0_output", |
| 246 | "mmc0_sample"; |
| 247 | }; |
| 248 | |
| 249 | mmc1_clk: clk@01c2008c { |
| 250 | #clock-cells = <1>; |
| 251 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
| 252 | reg = <0x01c2008c 0x4>; |
| 253 | clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
| 254 | clock-output-names = "mmc1", |
| 255 | "mmc1_output", |
| 256 | "mmc1_sample"; |
| 257 | }; |
| 258 | |
| 259 | mmc2_clk: clk@01c20090 { |
| 260 | #clock-cells = <1>; |
| 261 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
| 262 | reg = <0x01c20090 0x4>; |
| 263 | clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
| 264 | clock-output-names = "mmc2", |
| 265 | "mmc2_output", |
| 266 | "mmc2_sample"; |
| 267 | }; |
| 268 | |
| 269 | usb_clk: clk@01c200cc { |
| 270 | #clock-cells = <1>; |
| 271 | #reset-cells = <1>; |
| 272 | compatible = "allwinner,sun8i-h3-usb-clk"; |
| 273 | reg = <0x01c200cc 0x4>; |
| 274 | clocks = <&osc24M>; |
| 275 | clock-output-names = "usb_phy0", "usb_phy1", |
| 276 | "usb_phy2", "usb_phy3", |
| 277 | "usb_ohci0", "usb_ohci1", |
| 278 | "usb_ohci2", "usb_ohci3"; |
| 279 | }; |
| 280 | |
| 281 | mbus_clk: clk@01c2015c { |
| 282 | #clock-cells = <0>; |
| 283 | compatible = "allwinner,sun8i-a23-mbus-clk"; |
| 284 | reg = <0x01c2015c 0x4>; |
| 285 | clocks = <&osc24M>, <&pll6 1>, <&pll5>; |
| 286 | clock-output-names = "mbus"; |
| 287 | }; |
| 288 | }; |
| 289 | |
| 290 | soc { |
| 291 | compatible = "simple-bus"; |
| 292 | #address-cells = <1>; |
| 293 | #size-cells = <1>; |
| 294 | ranges; |
| 295 | |
| 296 | dma: dma-controller@01c02000 { |
| 297 | compatible = "allwinner,sun8i-h3-dma"; |
| 298 | reg = <0x01c02000 0x1000>; |
| 299 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 300 | clocks = <&bus_gates 6>; |
| 301 | resets = <&bus_rst 6>; |
| 302 | #dma-cells = <1>; |
| 303 | }; |
| 304 | |
| 305 | mmc0: mmc@01c0f000 { |
| 306 | compatible = "allwinner,sun5i-a13-mmc"; |
| 307 | reg = <0x01c0f000 0x1000>; |
| 308 | clocks = <&bus_gates 8>, |
| 309 | <&mmc0_clk 0>, |
| 310 | <&mmc0_clk 1>, |
| 311 | <&mmc0_clk 2>; |
| 312 | clock-names = "ahb", |
| 313 | "mmc", |
| 314 | "output", |
| 315 | "sample"; |
| 316 | resets = <&bus_rst 8>; |
| 317 | reset-names = "ahb"; |
| 318 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 319 | status = "disabled"; |
| 320 | #address-cells = <1>; |
| 321 | #size-cells = <0>; |
| 322 | }; |
| 323 | |
| 324 | mmc1: mmc@01c10000 { |
| 325 | compatible = "allwinner,sun5i-a13-mmc"; |
| 326 | reg = <0x01c10000 0x1000>; |
| 327 | clocks = <&bus_gates 9>, |
| 328 | <&mmc1_clk 0>, |
| 329 | <&mmc1_clk 1>, |
| 330 | <&mmc1_clk 2>; |
| 331 | clock-names = "ahb", |
| 332 | "mmc", |
| 333 | "output", |
| 334 | "sample"; |
| 335 | resets = <&bus_rst 9>; |
| 336 | reset-names = "ahb"; |
| 337 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 338 | status = "disabled"; |
| 339 | #address-cells = <1>; |
| 340 | #size-cells = <0>; |
| 341 | }; |
| 342 | |
| 343 | mmc2: mmc@01c11000 { |
| 344 | compatible = "allwinner,sun5i-a13-mmc"; |
| 345 | reg = <0x01c11000 0x1000>; |
| 346 | clocks = <&bus_gates 10>, |
| 347 | <&mmc2_clk 0>, |
| 348 | <&mmc2_clk 1>, |
| 349 | <&mmc2_clk 2>; |
| 350 | clock-names = "ahb", |
| 351 | "mmc", |
| 352 | "output", |
| 353 | "sample"; |
| 354 | resets = <&bus_rst 10>; |
| 355 | reset-names = "ahb"; |
| 356 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 357 | status = "disabled"; |
| 358 | #address-cells = <1>; |
| 359 | #size-cells = <0>; |
| 360 | }; |
| 361 | |
| 362 | usbphy: phy@01c19400 { |
| 363 | compatible = "allwinner,sun8i-h3-usb-phy"; |
| 364 | reg = <0x01c19400 0x2c>, |
| 365 | <0x01c1a800 0x4>, |
| 366 | <0x01c1b800 0x4>, |
| 367 | <0x01c1c800 0x4>, |
| 368 | <0x01c1d800 0x4>; |
| 369 | reg-names = "phy_ctrl", |
| 370 | "pmu0", |
| 371 | "pmu1", |
| 372 | "pmu2", |
| 373 | "pmu3"; |
| 374 | clocks = <&usb_clk 8>, |
| 375 | <&usb_clk 9>, |
| 376 | <&usb_clk 10>, |
| 377 | <&usb_clk 11>; |
| 378 | clock-names = "usb0_phy", |
| 379 | "usb1_phy", |
| 380 | "usb2_phy", |
| 381 | "usb3_phy"; |
| 382 | resets = <&usb_clk 0>, |
| 383 | <&usb_clk 1>, |
| 384 | <&usb_clk 2>, |
| 385 | <&usb_clk 3>; |
| 386 | reset-names = "usb0_reset", |
| 387 | "usb1_reset", |
| 388 | "usb2_reset", |
| 389 | "usb3_reset"; |
| 390 | status = "disabled"; |
| 391 | #phy-cells = <1>; |
| 392 | }; |
| 393 | |
| 394 | ehci1: usb@01c1b000 { |
| 395 | compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
| 396 | reg = <0x01c1b000 0x100>; |
| 397 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 398 | clocks = <&bus_gates 25>, <&bus_gates 29>; |
| 399 | resets = <&bus_rst 25>, <&bus_rst 29>; |
| 400 | phys = <&usbphy 1>; |
| 401 | phy-names = "usb"; |
| 402 | status = "disabled"; |
| 403 | }; |
| 404 | |
| 405 | ohci1: usb@01c1b400 { |
| 406 | compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
| 407 | reg = <0x01c1b400 0x100>; |
| 408 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 409 | clocks = <&bus_gates 29>, <&bus_gates 25>, |
| 410 | <&usb_clk 17>; |
| 411 | resets = <&bus_rst 29>, <&bus_rst 25>; |
| 412 | phys = <&usbphy 1>; |
| 413 | phy-names = "usb"; |
| 414 | status = "disabled"; |
| 415 | }; |
| 416 | |
| 417 | ehci2: usb@01c1c000 { |
| 418 | compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
| 419 | reg = <0x01c1c000 0x100>; |
| 420 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 421 | clocks = <&bus_gates 26>, <&bus_gates 30>; |
| 422 | resets = <&bus_rst 26>, <&bus_rst 30>; |
| 423 | phys = <&usbphy 2>; |
| 424 | phy-names = "usb"; |
| 425 | status = "disabled"; |
| 426 | }; |
| 427 | |
| 428 | ohci2: usb@01c1c400 { |
| 429 | compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
| 430 | reg = <0x01c1c400 0x100>; |
| 431 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 432 | clocks = <&bus_gates 30>, <&bus_gates 26>, |
| 433 | <&usb_clk 18>; |
| 434 | resets = <&bus_rst 30>, <&bus_rst 26>; |
| 435 | phys = <&usbphy 2>; |
| 436 | phy-names = "usb"; |
| 437 | status = "disabled"; |
| 438 | }; |
| 439 | |
| 440 | ehci3: usb@01c1d000 { |
| 441 | compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
| 442 | reg = <0x01c1d000 0x100>; |
| 443 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 444 | clocks = <&bus_gates 27>, <&bus_gates 31>; |
| 445 | resets = <&bus_rst 27>, <&bus_rst 31>; |
| 446 | phys = <&usbphy 3>; |
| 447 | phy-names = "usb"; |
| 448 | status = "disabled"; |
| 449 | }; |
| 450 | |
| 451 | ohci3: usb@01c1d400 { |
| 452 | compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
| 453 | reg = <0x01c1d400 0x100>; |
| 454 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 455 | clocks = <&bus_gates 31>, <&bus_gates 27>, |
| 456 | <&usb_clk 19>; |
| 457 | resets = <&bus_rst 31>, <&bus_rst 27>; |
| 458 | phys = <&usbphy 3>; |
| 459 | phy-names = "usb"; |
| 460 | status = "disabled"; |
| 461 | }; |
| 462 | |
| 463 | pio: pinctrl@01c20800 { |
| 464 | compatible = "allwinner,sun8i-h3-pinctrl"; |
| 465 | reg = <0x01c20800 0x400>; |
| 466 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 467 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 468 | clocks = <&bus_gates 69>; |
| 469 | gpio-controller; |
| 470 | #gpio-cells = <3>; |
| 471 | interrupt-controller; |
| 472 | #interrupt-cells = <2>; |
| 473 | |
| 474 | uart0_pins_a: uart0@0 { |
| 475 | allwinner,pins = "PA4", "PA5"; |
| 476 | allwinner,function = "uart0"; |
| 477 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 478 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 479 | }; |
| 480 | |
| 481 | mmc0_pins_a: mmc0@0 { |
| 482 | allwinner,pins = "PF0", "PF1", "PF2", "PF3", |
| 483 | "PF4", "PF5"; |
| 484 | allwinner,function = "mmc0"; |
| 485 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 486 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 487 | }; |
| 488 | |
| 489 | mmc0_cd_pin: mmc0_cd_pin@0 { |
| 490 | allwinner,pins = "PF6"; |
| 491 | allwinner,function = "gpio_in"; |
| 492 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 493 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
| 494 | }; |
| 495 | |
| 496 | mmc1_pins_a: mmc1@0 { |
| 497 | allwinner,pins = "PG0", "PG1", "PG2", "PG3", |
| 498 | "PG4", "PG5"; |
| 499 | allwinner,function = "mmc1"; |
| 500 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 501 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 502 | }; |
| 503 | }; |
| 504 | |
| 505 | bus_rst: reset@01c202c0 { |
| 506 | #reset-cells = <1>; |
| 507 | compatible = "allwinner,sun8i-h3-bus-reset"; |
| 508 | reg = <0x01c202c0 0x1c>; |
| 509 | }; |
| 510 | |
| 511 | timer@01c20c00 { |
| 512 | compatible = "allwinner,sun4i-a10-timer"; |
| 513 | reg = <0x01c20c00 0xa0>; |
| 514 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 515 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 516 | clocks = <&osc24M>; |
| 517 | }; |
| 518 | |
| 519 | wdt0: watchdog@01c20ca0 { |
| 520 | compatible = "allwinner,sun6i-a31-wdt"; |
| 521 | reg = <0x01c20ca0 0x20>; |
| 522 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 523 | }; |
| 524 | |
| 525 | uart0: serial@01c28000 { |
| 526 | compatible = "snps,dw-apb-uart"; |
| 527 | reg = <0x01c28000 0x400>; |
| 528 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| 529 | reg-shift = <2>; |
| 530 | reg-io-width = <4>; |
| 531 | clocks = <&bus_gates 112>; |
| 532 | resets = <&bus_rst 144>; |
| 533 | dmas = <&dma 6>, <&dma 6>; |
| 534 | dma-names = "rx", "tx"; |
| 535 | status = "disabled"; |
| 536 | }; |
| 537 | |
| 538 | uart1: serial@01c28400 { |
| 539 | compatible = "snps,dw-apb-uart"; |
| 540 | reg = <0x01c28400 0x400>; |
| 541 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 542 | reg-shift = <2>; |
| 543 | reg-io-width = <4>; |
| 544 | clocks = <&bus_gates 113>; |
| 545 | resets = <&bus_rst 145>; |
| 546 | dmas = <&dma 7>, <&dma 7>; |
| 547 | dma-names = "rx", "tx"; |
| 548 | status = "disabled"; |
| 549 | }; |
| 550 | |
| 551 | uart2: serial@01c28800 { |
| 552 | compatible = "snps,dw-apb-uart"; |
| 553 | reg = <0x01c28800 0x400>; |
| 554 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 555 | reg-shift = <2>; |
| 556 | reg-io-width = <4>; |
| 557 | clocks = <&bus_gates 114>; |
| 558 | resets = <&bus_rst 146>; |
| 559 | dmas = <&dma 8>, <&dma 8>; |
| 560 | dma-names = "rx", "tx"; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | |
| 564 | uart3: serial@01c28c00 { |
| 565 | compatible = "snps,dw-apb-uart"; |
| 566 | reg = <0x01c28c00 0x400>; |
| 567 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 568 | reg-shift = <2>; |
| 569 | reg-io-width = <4>; |
| 570 | clocks = <&bus_gates 115>; |
| 571 | resets = <&bus_rst 147>; |
| 572 | dmas = <&dma 9>, <&dma 9>; |
| 573 | dma-names = "rx", "tx"; |
| 574 | status = "disabled"; |
| 575 | }; |
| 576 | |
| 577 | gic: interrupt-controller@01c81000 { |
| 578 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 579 | reg = <0x01c81000 0x1000>, |
| 580 | <0x01c82000 0x1000>, |
| 581 | <0x01c84000 0x2000>, |
| 582 | <0x01c86000 0x2000>; |
| 583 | interrupt-controller; |
| 584 | #interrupt-cells = <3>; |
| 585 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 586 | }; |
| 587 | |
| 588 | rtc: rtc@01f00000 { |
| 589 | compatible = "allwinner,sun6i-a31-rtc"; |
| 590 | reg = <0x01f00000 0x54>; |
| 591 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 592 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 593 | }; |
| 594 | }; |
| 595 | }; |