Simon Glass | 6b1ba98 | 2014-12-29 19:32:28 -0700 | [diff] [blame^] | 1 | config VIDEO_VESA |
| 2 | bool "Enable VESA video driver support" |
| 3 | depends on X86 |
| 4 | default n |
| 5 | help |
| 6 | Turn on this option to enable a very simple driver which uses vesa |
| 7 | to discover the video mode and then provides a frame buffer for use |
| 8 | by U-Boot. This can in principle be used with any platform that |
| 9 | supports PCI and video cards that support VESA BIOS Extension (VBE). |
| 10 | |
Bin Meng | ade8127 | 2015-01-06 22:14:21 +0800 | [diff] [blame] | 11 | config VIDEO_X86 |
| 12 | bool "Enable x86 video driver support" |
| 13 | depends on X86 |
| 14 | default n |
| 15 | help |
| 16 | Turn on this option to enable a very simple driver which uses vesa |
| 17 | to discover the video mode and then provides a frame buffer for use |
| 18 | by U-Boot. |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 19 | |
| 20 | config VIDEO_LCD_SSD2828 |
| 21 | bool "SSD2828 bridge chip" |
| 22 | default n |
| 23 | ---help--- |
| 24 | Support for the SSD2828 bridge chip, which can take pixel data coming |
| 25 | from a parallel LCD interface and translate it on the fly into MIPI DSI |
| 26 | interface for driving a MIPI compatible LCD panel. It uses SPI for |
| 27 | configuration. |
| 28 | |
| 29 | config VIDEO_LCD_SSD2828_TX_CLK |
| 30 | int "SSD2828 TX_CLK frequency (in MHz)" |
| 31 | depends on VIDEO_LCD_SSD2828 |
Siarhei Siamashka | dddccd6 | 2015-01-19 05:23:35 +0200 | [diff] [blame] | 32 | default 0 |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 33 | ---help--- |
| 34 | The frequency of the crystal, which is clocking SSD2828. It may be |
| 35 | anything in the 8MHz-30MHz range and the exact value should be |
| 36 | retrieved from the board schematics. Or in the case of Allwinner |
| 37 | hardware, it can be usually found as 'lcd_xtal_freq' variable in |
Siarhei Siamashka | dddccd6 | 2015-01-19 05:23:35 +0200 | [diff] [blame] | 38 | FEX files. It can be also set to 0 for selecting PCLK from the |
| 39 | parallel LCD interface instead of TX_CLK as the PLL clock source. |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 40 | |
| 41 | config VIDEO_LCD_SSD2828_RESET |
| 42 | string "RESET pin of SSD2828" |
| 43 | depends on VIDEO_LCD_SSD2828 |
| 44 | default "" |
| 45 | ---help--- |
| 46 | The reset pin of SSD2828 chip. This takes a string in the format |
| 47 | understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. |
| 48 | |
Hans de Goede | a5464f2 | 2015-01-20 09:22:26 +0100 | [diff] [blame] | 49 | config VIDEO_LCD_HITACHI_TX18D42VM |
| 50 | bool "Hitachi tx18d42vm LVDS LCD panel support" |
| 51 | depends on VIDEO |
| 52 | default n |
| 53 | ---help--- |
| 54 | Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a |
| 55 | lcd controller which needs to be initialized over SPI, once that is |
| 56 | done they work like a regular LVDS panel. |
| 57 | |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 58 | config VIDEO_LCD_SPI_CS |
| 59 | string "SPI CS pin for LCD related config job" |
Hans de Goede | a5464f2 | 2015-01-20 09:22:26 +0100 | [diff] [blame] | 60 | depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 61 | default "" |
| 62 | ---help--- |
| 63 | This is one of the SPI communication pins, involved in setting up a |
| 64 | working LCD configuration. The exact role of SPI may differ for |
| 65 | different hardware setups. The option takes a string in the format |
| 66 | understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. |
| 67 | |
| 68 | config VIDEO_LCD_SPI_SCLK |
| 69 | string "SPI SCLK pin for LCD related config job" |
Hans de Goede | a5464f2 | 2015-01-20 09:22:26 +0100 | [diff] [blame] | 70 | depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 71 | default "" |
| 72 | ---help--- |
| 73 | This is one of the SPI communication pins, involved in setting up a |
| 74 | working LCD configuration. The exact role of SPI may differ for |
| 75 | different hardware setups. The option takes a string in the format |
| 76 | understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. |
| 77 | |
| 78 | config VIDEO_LCD_SPI_MOSI |
| 79 | string "SPI MOSI pin for LCD related config job" |
Hans de Goede | a5464f2 | 2015-01-20 09:22:26 +0100 | [diff] [blame] | 80 | depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM |
Siarhei Siamashka | b8329ac | 2015-01-19 05:23:32 +0200 | [diff] [blame] | 81 | default "" |
| 82 | ---help--- |
| 83 | This is one of the SPI communication pins, involved in setting up a |
| 84 | working LCD configuration. The exact role of SPI may differ for |
| 85 | different hardware setups. The option takes a string in the format |
| 86 | understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. |
| 87 | |
| 88 | config VIDEO_LCD_SPI_MISO |
| 89 | string "SPI MISO pin for LCD related config job (optional)" |
| 90 | depends on VIDEO_LCD_SSD2828 |
| 91 | default "" |
| 92 | ---help--- |
| 93 | This is one of the SPI communication pins, involved in setting up a |
| 94 | working LCD configuration. The exact role of SPI may differ for |
| 95 | different hardware setups. If wired up, this pin may provide additional |
| 96 | useful functionality. Such as bi-directional communication with the |
| 97 | hardware and LCD panel id retrieval (if the panel can report it). The |
| 98 | option takes a string in the format understood by 'name_to_gpio' |
| 99 | function, e.g. PH1 for pin 1 of port H. |